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Getting Started with Targeting Xilinx Versal ACAP Platform

This example shows how to use HDL Coder™ and the hardware-software codesign workflow to blink LEDs at various frequencies on the Xilinx® Versal® ACAP platform.


This example is a step-by-step guide that helps you use HDL Coder to generate a custom HDL IP core that blinks LEDs on the Xilinx Versal AI Core Series VCK190 Evaluation Kit. It also shows you how to build a bitstream and program the Versal device using the hardware-software codesign workflow.

You can use the hardware-software codesign workflow to help automate the deployment of your MATLAB® and Simulink® design to a Xilinx Versal ACAP device. You can explore the best ways to partition and deploy your design by iterating through this workflow. The following diagram shows a high-level picture of generating an IP core and bitstream, a step in the hardware-software codesign workflow. For more information, see Targeting FPGA & SoC Hardware Overview.

You can use MATLAB and Simulink to design, simulate, and verify your application, perform what-if scenarios with algorithms, and optimize parameters. Using the guided workflow shown in this example, you can then automatically generate HDL code for the programmable logic using HDL Coder, and implement the design on the Xilinx Versal ACAP Platform.

In this workflow, you perform the following steps:

  1. Set up your Xilinx Versal VCK190 hardware and tools.

  2. Generate an HDL IP core using HDL Workflow Advisor.

  3. Integrate the IP core into a Xilinx Vivado project and program the Xilinx Versal hardware.

  4. Run FPGA IO commands to write into AXI registers in Fabric from MATLAB Command Line


  1. Xilinx Vivado Design Suite, with the supported version listed in HDL Language Support and Supported Third-Party Tools and Hardware

  2. Xilinx Versal AI Core Series VCK190 Evaluation Kit

  3. HDL Coder Support Package for Xilinx Versal Platform

Set Up Xilinx Versal ACAP Hardware and Tools

1. Set up the Xilinx Versal AI Core Series VCK190 Evaluation Kit as shown in the following figure. To learn more about the VCK190 hardware setup, please refer to the Xilinx VCK190 Board User Guide.

2. Connect your computer to the USB JTAG/UART connector of VCK190 using a Micro USB cable.

3. Install the HDL Coder Support Packages for Xilinx Versal Platform if you have not already.

4. Set up the Xilinx Vivado synthesis tool path using the following command in the MATLAB command window. Use your own Vivado installation path when you run the command.

hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', 'C:\Xilinx\Vivado\2022.1\bin\vivado.bat');

Generate HDL IP Core Using HDL Workflow Advisor

Generating an IP core using the HDL Workflow Advisor enables you to automatically generate a sharable and reusable IP core module from a Simulink model. The generated IP core is designed to be connected to an embedded processor on an FPGA device. HDL Coder generates HDL code from the Simulink blocks, and also generates HDL code for the AXI interface logic connecting the IP core to the embedded processor. HDL Coder packages all the generated files into an IP core folder. You can then integrate the generated IP core with a larger FPGA embedded design in the Xilinx Vivado environment.

In this example, the subsystem led_counter is the hardware subsystem. It models a counter that blinks the LEDs on an FPGA board. Two input ports, Blink_frequency and Blink_direction, are control ports that determine the LED blink frequency and direction.


1. Start the IP core generation workflow.

1.1. Open the HDL Workflow Advisor from the led_counter subsystem by right-clicking the led_counter subsystem and choosing HDL Code > HDL Workflow Advisor.

1.2. In the Set Target > Set Target Device and Synthesis Tool task, for Target workflow, select IP Core Generation.

1.3. For Target platform, select Xilinx Versal AI Core Series VCK190 Evaluation Kit. If you do not have this option, select Get more to open the Support Package Installer. In the Support Package Installer, select Xilinx Versal Platform and follow the instructions provided by the Support Package Installer to complete the installation.

1.4. Click Run This Task to run the Set Target Device and Synthesis Tool task.

1.5 In the Set Target > Set Target Reference Design task, choose Default system.

1.6. Click Run This Task to run the Set Target Reference Design task.

2. Configure the target interface.

Map each port in your DUT to one of the IP core target interfaces. In this example, input ports Blink_frequency and Blink_direction are mapped to the AXI4-Lite interface, so HDL Coder generates AXI interface accessible registers for them. The LED output port is mapped to an external interface, LEDs General Purpose [0:3], which connects to the LED hardware on the Versal board.

2.1 In the Set Target > Set Target Interface task, choose AXI4-Lite for Blink_frequency, Blink_direction, and Read_back.

2.2 Choose LEDs General Purpose [0:3] for LED.

2.3 In the Set Target > Set Target Frequency task, set Target Frequency to 50 MHz.

3. Generate the IP core.

To generate the IP core, right-click the Generate RTL Code and IP Core task and select Run to Selected Task.

4. Generate and view the IP core report.

After you generate the custom IP core, the IP core files are in the ipcore folder within your project folder. An HTML custom IP core report is generated together with the custom IP core. The report describes the behavior and contents of the generated custom IP core.

Integrate IP Core with Xilinx Vivado Environment

In this part of the workflow, you insert your generated IP core into a embedded system reference design, generate an FPGA bitstream, and download the bitstream to the Versal hardware.

The reference design is a predefined Xilinx Vivado project. It contains all the elements the Xilinx software needs to deploy your design to the Versal platform, except for the custom IP core and embedded software that you generate.

1. To integrate with the Xilinx Vivado environment, select the Create Project task under Embedded System Integration and click Run This Task. A Xilinx Vivado project with IP Integrator embedded design is generated.

A link to the project is provided in the dialog window. You can optionally open up the project to take a look. From the block diagram in Vivado tool, you can see the HDL Coder generated IP core led_count_ip_0 is connected to the Processing System through the AXI interface.

% 2. To generate Host Interface Scripts, select checkbox Generate host interface script in task Generate Software Interface and Click Run This Task. The script contains the DUT ports and interface mapping information, which HDL Coder uses to create the AXI drivers and access the HDL IP core.

The host interface script contains commands that enable you to connect to the target hardware and to write to or read from the generated IP core by using the AXI driver blocks or the AXI Manager.

3. Build the FPGA bitstream in the Build FPGA Bitstream task. Make sure the Run build process externally option is checked, so the Xilinx synthesis tool runs in a separate process from MATLAB. Wait for the synthesis tool process to finish running in the external command window.

4. After the bitstream is generated, select the Program Target Device task. Choose Download for Programming method to program the FPGA bitstream through Download mode to the Xilinx Versal VCK190 board. Click Run This Task to program the Versal hardware. Generated bitstream will be copied to SD card connected to Versal hardware.

After you program the FPGA hardware, the LED starts blinking on your Xilinx Versal VCK190 board.

Run FPGA IO Commands to read from and write to AXI Registers

When you run the IP core generation workflow and enable Generate host interface script option, two MATLAB files, gs_hdlcoder_led_blinking_4bit_interface.m and gs_hdlcoder_led_blinking_4bit_setup.m, are generated:

gs_hdlcoder_led_blinking_4bit_interface.m - This interface script creates a target object, instantiates the setup script and connects to the target hardware. The script sends read and write commands to the generated HDL IP core.

gs_hdlcoder_led_blinking_4bit_setup.m - This setup function adds the AXI4 slave and AXI4-Stream interfaces. The script also contains DUT port objects that have the port name, direction, data type, and interface mapping information. The script maps the DUT ports to the corresponding interfaces.

Follow these steps to access data from the AXI Register by using readPort and writePort commands:

1. Set up the Zynq hardware connection by entering the this command in the MATLAB command window.

   hProcessor = xilinxsoc()

The xilinxsoc function logs in to the hardware via COM port and runs the ifconfig command to obtain the IP address of the board. This function also tests the ethernet connection. You can also run this command with board IP address as shown in interface script.

2. Create a FPGA object by running this command

   hFPGA = fpga(hProcessor)

3. Run gs_hdlcoder_led_blinking_4bit_setup(hFPGA) setup function. This function configures the FPGA object with the same interfaces as the generated IP core.

4. Run writePort command to change the blinking frequency of LEDs.

   writePort(hFPGA, "Blink_frequency", 6)

5. Use readPort command to read the values from the read back register.You can read "Read_back" value multiple times to observe changing value of Read_back register.

   data_Read_back = readPort(hFPGA, "Read_back")