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Locate Numeric Differences After Speed Optimization

This example shows how a model that contains Trigonometric Function blocks might have differences in numeric results after HDL code generation. You can observe these numeric differences in the generated validation model. The validation model compares the original model with the generated model that shows the effect of block implementations and speed and area optimizations.

Trigonometric Function Model

Open the model hdlcoder_sincos_cordic_optimization.

open_system('hdlcoder_sincos_cordic_optimization')
set_param('hdlcoder_sincos_cordic_optimization', 'SimulationCommand', 'Update')

Inside the HDL_DUT subsystem, this model uses Trigonometric Function blocks that have HDL architecture set to CORDIC and LatencyStrategy set to MAX. The block settings introduce pipelines at the input of the Trigonometric Function blocks.

open_system('hdlcoder_sincos_cordic_optimization/HDL_DUT')

The model has optimizations such as hierarchical distributed pipelining enabled on the model. To see the HDL parameters saved on the model, use the hdlsaveparams function.

hdlsaveparams('hdlcoder_sincos_cordic_optimization')
%% Set Model 'hdlcoder_sincos_cordic_optimization' HDL parameters
hdlset_param('hdlcoder_sincos_cordic_optimization', 'ClockRatePipelining', 'off');
hdlset_param('hdlcoder_sincos_cordic_optimization', 'EDAScriptGeneration', 'off');
hdlset_param('hdlcoder_sincos_cordic_optimization', 'EnableTestpoints', 'on');
hdlset_param('hdlcoder_sincos_cordic_optimization', 'GenerateCoSimModel', 'ModelSim');
hdlset_param('hdlcoder_sincos_cordic_optimization', 'GenerateValidationModel', 'on');
hdlset_param('hdlcoder_sincos_cordic_optimization', 'HDLGenerateWebview', 'on');
hdlset_param('hdlcoder_sincos_cordic_optimization', 'HDLSubsystem', 'hdlcoder_sincos_cordic_optimization/sin_cordic');
hdlset_param('hdlcoder_sincos_cordic_optimization', 'HDLSynthCmd', 'set_global_assignment -name VHDL_FILE "$src_dir/%s"\n');
hdlset_param('hdlcoder_sincos_cordic_optimization', 'HDLSynthFilePostfix', '_quartus.tcl');
hdlset_param('hdlcoder_sincos_cordic_optimization', 'HDLSynthInit', 'load_package flow\nset top_level %s\nset src_dir "[pwd]"\nset prj_dir "q2dir"\nfile mkdir ../$prj_dir\ncd ../$prj_dir\nproject_new $top_level -revision $top_level -overwrite\nset_global_assignment -name FAMILY "Cyclone IV"\nset_global_assignment -name DEVICE EP4CE115F29C7\nset_global_assignment -name TOP_LEVEL_ENTITY $top_level\n');
hdlset_param('hdlcoder_sincos_cordic_optimization', 'HDLSynthTerm', 'execute_flow -compile\nproject_close\n');
hdlset_param('hdlcoder_sincos_cordic_optimization', 'HDLSynthTool', 'Quartus');
hdlset_param('hdlcoder_sincos_cordic_optimization', 'HierarchicalDistPipelining', 'on');
hdlset_param('hdlcoder_sincos_cordic_optimization', 'MaskParameterAsGeneric', 'on');
hdlset_param('hdlcoder_sincos_cordic_optimization', 'MinimizeClockEnables', 'on');
hdlset_param('hdlcoder_sincos_cordic_optimization', 'MinimizeIntermediateSignals', 'on');
hdlset_param('hdlcoder_sincos_cordic_optimization', 'OptimizationReport', 'on');
hdlset_param('hdlcoder_sincos_cordic_optimization', 'ResetType', 'Synchronous');
hdlset_param('hdlcoder_sincos_cordic_optimization', 'ResourceReport', 'on');
hdlset_param('hdlcoder_sincos_cordic_optimization', 'ShareAdders', 'on');
hdlset_param('hdlcoder_sincos_cordic_optimization', 'TargetLanguage', 'Verilog');
hdlset_param('hdlcoder_sincos_cordic_optimization', 'Traceability', 'on');

hdlset_param('hdlcoder_sincos_cordic_optimization/HDL_DUT/Trigonometric Function', 'Architecture', 'Cordic');

hdlset_param('hdlcoder_sincos_cordic_optimization/HDL_DUT/Trigonometric Function1', 'Architecture', 'Cordic');

Generate HDL Code and Validation Model

To see the effect of the optimization, generate HDL code and validation model for the HDL_DUT subsystem by using the makehdl function.

makehdl('hdlcoder_sincos_cordic_optimization')

When you open the HDL Check Report, you see a warning message displayed that indicates delays introduced at the inputs of the blocks, which might cause a numeric mismatch in the initial cycles when simulating the validation model.

After code generation, you see the model gm_hdlcoder_sincos_cordic_optimization_vnl. In this example, the model has been saved with the name hdlcoder_sincos_cordic_optimization_validation.

open_system('hdlcoder_sincos_cordic_optimization_validation')
set_param('hdlcoder_sincos_cordic_optimization_validation', 'SimulationCommand', 'Update')

Observe Numeric Differences

The HDL_DUT subsystem highlighted in cyan indicates that this subsystem is different from the subsystem in the original model HDL_DUT_vnl. The HDL_DUT subsystem is part of the generated model after HDL code generation, and shows the effect of optimizations. You also see the pipelines introduced by the Trigonmetric Function blocks.

open_system('hdlcoder_sincos_cordic_optimization_validation/HDL_DUT')

When you simulate the model, you see assertions detected in the initial cycles of simulation, which indicates a numeric mismatch. The mismatch is caused by pipelines introduced at the input of the block. To fix the mismatch, avoid using block implementations, or HDL block properties such as InputPipeline, or optimizations that introduce pipelines at the input of the blocks.

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