## Supported MATLAB Data Types, Operators, and Control Flow Statements

When you generate HDL and SystemC code from your MATLAB^{®} algorithm, use the data types, operators, and control flow statements that
HDL Coder™ supports.

### Supported Data Types

HDL Coder does not support cell arrays and `Inf`

data types.
This table shows the supported subset of MATLAB data types.

Types | Supported Data Types | Restrictions |
---|---|---|

Integer |
`uint8` ,`uint16` ,`uint32` ,`uint64` `int8` ,`int16` ,`int32` ,`int64`
| In Simulink^{®}, MATLAB Function block ports must use
numeric types `sfix64` or `ufix64`
for 64-bit data. |

Real |
`double` `single`
| HDL code generated with
Real data types are not supported for SystemC code generation. |

Character | `char` | – |

Logical |
| – |

Fixed point |
Scaled (binary point only) fixed-point numbers Custom integers (zero binary point)
| Fixed-point numbers with slope (not equal to 1.0) and bias (not equal to 0.0) are not supported. Maximum word size for fixed-point numbers is 128 bits. |

Vectors |
unordered `{N}` row `{1, N}` column `{N, 1}`
| The maximum number of vector elements allowed is 2^32. Before a variable is subscripted, it must be fully defined. |

Matrices |
| Matrices are supported in the body of the design algorithm, but are not supported as inputs to the top-level design function. Do not use matrices in the testbench. |

Structures | `struct` | Arrays of structures are not supported. For the FPGA Turnkey and IP Core Generation workflows, structures are supported in the body of the design algorithm, but are not supported as inputs to the top-level design function. Structures are not supported as inputs and outputs at the top-level DUT ports for SystemC code generation. |

Enumerations | `enumeration` | Enumeration values must be monotonically increasing. If your target language is Verilog Enumerations at the top-level DUT ports are not supported with the following workflows or verification methods: IP Core Generation workflow FPGA Turnkey workflow FPGA-in-the-Loop HDL Cosimulation SystemC Code Generation Workflow
Enumerations are not supported as inputs and outputs at the top-level DUT ports for SystemC code generation. |

Global variables are not supported for HDL and SystemC code generation.

### Supported Operators

**Note**

HDL and SystemC code generated for large vector and matrix inputs to arithmetic operations can result in inefficient code. The code for these operators is not automatically pipelined.

**Arithmetic Operators**

Operation | Operator Syntax | Equivalent Function | Restrictions |
---|---|---|---|

Binary addition | `A+B ` | `plus(A,B) ` | Neither `A` nor `B` can be data
type `logical` . |

Matrix multiplication | `A*B ` | `mtimes(A,B) ` | HDL code generated for matrix arithmetic operations is not pipelined, and can result in inefficient code. |

Arraywise multiplication | `A.*B ` | `times(A,B)`
| Neither `A` nor `B` can be data
type `logical` . |

Matrix power | `A^B`
| `mpower(A,B) ` |
HDL code generated for matrix arithmetic operations is not pipelined, and can result in inefficient code. |

Arraywise power | `A.^B ` | `power(A,B) ` | `A` and `B` must be scalar, and
`B` must be an integer. |

Complex transpose | `A'`
| `ctranspose(A) ` | – |

Matrix transpose | `A.'`
| `transpose(A) ` | |

Matrix concat | `[A B] ` | None | – |

Matrix index | `A(r c) ` | None | Before you use a variable, you must fully define it. |

**Logical Operators**

Operation | Operator Syntax | M Function Equivalent | Notes |
---|---|---|---|

Logical And | `A&B` | `and(A,B)` | – |

Logical Or | `A|B` | `or(A,B)` | – |

Logical Xor | `A xor B` | `xor(A,B)` | – |

Logical And (short circuiting) | `A&&B` | N/A | Use short circuiting logical operators within conditionals. |

Logical Or (short circuiting) | `A||B` | N/A | Use short circuiting logical operators within conditionals. |

Element complement | `~A` | `not(A)` | – |

**Relational Operators**

Relation | Operator Syntax | Equivalent Function |
---|---|---|

Less than | `A<B ` | `lt(A,B) ` |

Less than or equal to | `A<=B ` | `le(A,B) ` |

Greater than or equal to | `A>=B ` | `ge(A,B) ` |

Greater than | `A>B ` | `gt(A,B) ` |

Equal | `A==B ` | `eq(A,B) ` |

Not equal | `A~=B ` | `ne(A,B) ` |

### Control Flow Statements

HDL Coder supports the following control flow statements and constructs with restrictions.

Control Flow Statement | Restrictions |
---|---|

| Do not use Do not use the HDL Coder does not support nonscalar expressions in the
conditions of |

`if ` | Do not use the HDL Coder does not support nonscalar expressions in the
conditions of |

`switch ` | The conditional expression in a `uint8` ,`uint16` ,`uint32` ,`int8` ,`int16` , or`int32` data typesScalar data
If multiple |

The following control flow statements are not supported:

`while`

`break`

`continue`

`return`

`parfor`

Avoid using the following vector functions, as they may generate loops containing
`break`

statements:

`isequal`

`bitrevorder`