You can designate internal signals in your model as test points and configure the SystemVerilog DPI generator to create one or more access functions. You can also enable logging on test points. Then you can use the generated test bench to compare the Simulink® data with values observed while running the SystemVerilog component.
Choose an internal signal in your model, following these guidelines:
Enable the test point at the source of the signal. If the test point is on a connecting signal, such as between subsystems, the signal might be optimized out of the generated code.
Select a signal that is not an input or output of your component. If you select an I/O signal, the generator does not provide an access function. Such an access function is redundant because you already have visibility of the I/O signals.
Complex signals are not supported.
Virtual signals and buses are not supported.
Continuous, asynchronous, and triggered sample times are not supported.
Multirate designs are not supported for signal logging. You can add a test point, and generate an access function. However, the test bench is single rate and cannot perform a comparison against logged data at different rates.
Model references are not supported. If you want to add a test point in a model reference, you first have to wire the signal out of the model reference. Once the signal is accessible in your model, you can select it as a test point.
In your model, right-click the signal and select Properties.
Select the Test point check box.
Give the test point a unique name in the Signal name box.
Optionally, select Log signal data. This check box enables the generated test bench to compare logged data from the model against values observed while running the generated component. The test bench uses the generated access functions to fetch the signal values during the simulation.
For more details on test points and logging in Simulink, see Configure Signals as Test Points (Simulink).
Open your model, and on the Apps tab, click HDL Verifier. Then, on the HDL Verifier tab, click C Code Settings. The Configuration Parameters dialog opens on Code Generation.
On the left pane, under Code Generation, select Interface.
In Generate C API for, ensure the signals check box is selected. The other check boxes do not affect the DPI component or test bench.
In the HDL Verifier tab, click SystemVerilog Settings.
For Generate access function to test point, select
One function per Test Point or
One function for all Test Points.
If you select
One function for all Test Points,
a single function returns values for all test points.
DPI_TestPointAccessFcn(input chandle objhandle,input real Name1,inout real Name2);
If you select
One function per Test Point, each
signal has a separate access function.
DPI_Name_TestPoint(input chandle objhandle,inout real Name);
If you select
None, the tool does not generate