DDR4 Memory Down Implementation Kit
Implement a DDR4 memory down (MD) interface for pre-layout analysis or post-layout verification.
This DDR4 MD implementation signal integrity kit includes all the transfer nets, timing models, waveform processing levels, and simulation models for both single and dual rank memory down (discrete) configurations. This includes buffer models for the DDR4 memory controller as well as Micron SDRAMs. Also included are timing models with complete waveform processing levels. This kit implements x16 SDRAM configurations only.
You can modify the kit to match your exact DDR4 implementation. Then, perform complete pre-layout solution space analysis and/or full post-layout verification for waveform quality and timing margins.
Open DDR4 MD Kit
Open the DDR4 MD kit in the Parallel Link Designer app using the
Project name: DDR4_MD
Interface names: dr_x16 and sr_x16
This kit supports both HSPICE and IsSpice4 simulators. No specific version of either simulator is required when running this kit.
For more information about the DDR4 MD implementation signal integrity kit, including block diagrams, system configurations, transfer nets and libraries, refer to the document DDR4_MD.pdf that is attached to this example as a supporting file.