To refine the dead logic in your model for dependency analysis, use the Model Slicer. To provide an accurate slice, Model Slicer leverages Simulink® Design Verifier™ dead logic analysis to remove the unreachable paths in the model. Model Slicer identifies the dead logic and refines the model slice for dependency analysis. For more information on Dead logic, see Dead Logic Detection (Simulink Design Verifier).
This example shows how to refine the model for dead logic. The
sldvSlicerdemo_dead_logic model consists of dead logic paths that you refine for dependency analysis.
1. Open the
sldvSlicerdemo_dead_logic model, and then select Analysis > Model Slicer.
Controller subsystem and add the outport
throt as the starting point.
The Model Slicer highlights the upstream dependency of the
2. In the Model Slice Manager, select Refine Dead Logic.
3. Click Get Dead Logic Data.
4. Specify the Analysis time and run the analysis. You can import existing dead logic results from the
sldvData file or load existing
.slslicex data for analysis. For more information, see Refine Highlighted Model by Using Existing .slslicex or Dead Logic Results.
set input is equal to
False input to switch is removed for dependency analysis. Similarly, the output of block
OR is always
true and removed from the model slice.