This example shows how to perform time-domain model verification using Simulink® Design Optimization™ Model Verification blocks. During time-domain verification, the software monitors a signal to check if it meets time-domain characteristics such as step response characteristics and upper and lower amplitudes, or tracks a reference signal.
You can also use blocks from Simulink and Simulink Control Design™ Model Verification libraries to design complex assertion logic for time-domain and frequency-domain verification, and signal monitoring. You can construct simulation tests for your model using the Verification Manager in the Signal Builder.
Open Simulink model.
sys = 'sldo_model1_stepblk'; open_system(sys);
The model includes a Step Response block which is a Check Step Response Characteristics block from the Simulink Design Optimization Model Verification library and has default step response bounds.
In the Simulink Editor, under Simulation, click Run.
The block asserts multiple times during simulation because the signal to which the block is connected violates the specified bounds. Assertion warnings appear in the MATLAB® command window.
You can optimize model parameters to satisfy the bounds and eliminate assertion warnings. See Design Optimization to Meet Step Response Requirements (GUI).