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Specify and Verify Design Requirements

R2026b
Verify design against requirements, refine counterexamples by using input assumptions

Safety requirements define undesired behaviors in a model. Simulink® Design Verifier™ uses property proving to verify that properties associated with model requirements hold under all possible input values or provides counterexamples that lead to violations. You use Simulink Design Verifier to model design requirements as properties and then Prove Properties in a Model.

Blocks

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Proof Assumption blockProof AssumptionConstrain signal values when proving model properties
Proof Objective blockProof ObjectiveDefine objectives that signals must satisfy when proving model properties
Assertion blockAssertionCheck whether signal is zero
Detector blockDetectorDetect true duration on input and construct output true duration based on output type
Extender blockExtenderExtend true duration of input
Implies blockImpliesSpecify condition that produces a certain response
Within Implies blockWithin ImpliesVerify response occurs within desired duration
Verification Subsystem blockVerification SubsystemSpecify proof or test objectives without impacting simulation results or generated code

Functions

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sldv.assumeProof assumption function for Stateflow charts and MATLAB Function blocks
sldv.proveProof objective function for Stateflow charts and MATLAB Function blocks
sldvextractExtract subsystem or subchart contents into new model for analysis
sldvoptionsCreate Simulink Design Verifier options object
sldvrunRun Simulink Design Verifier analysis on model
sldvreportGenerate Simulink Design Verifier report

Topics

Featured Examples