To detect division by zero and out of bound array access errors in a model with C/C++ custom code in model blocks or Stateflow® charts, use design error detection analysis. Simulink Design Verifier identifies the code that results in errors and then either proves that the errors are valid or generates test cases that replicate the error.
This example shows how to detect division by zero errors in a model that consists of C/C++ code in a Stateflow® chart.
The example model
sldvexCustomCodeErrorDetectionExample contains a Stateflow® chart that calls C/C++ custom code that uses input and output buses.
To perform design error detection analysis, on the Design Verifier tab, click Detect Design Errors. After the analysis completes, the Results Summary window indicates that one objective is falsified.
On the Design Verifier tab, in the Review Results section, click Highlight in Model. To view the C/C++ run-time error objectives that resulted in the error, click on the Simulink® Editor. The Results Inspector window displays the division by zero objectives.
Note: When you click View test case for the Error - needs simulation objective, Simulink® Design Verifier™ displays the test case that replicates the error. If you simulate the test case, MATLAB® may crash during custom code analysis.
To view the HTML report, on the Design Verifier tab, click HTML Report. The Design Error Detection Objectives Status section in the report describes the falsified objective.
In the example model, right-click the Saturation block that is greyed out and Uncomment the block. Reanalyze the model, by clicking Detect Design Errors. The results show that the C/C++ run-time objective is valid.
To complete the example, close the model.