Assess Model Simulation Using verify
Statements
You can verify model simulation by using verify
statements in the
Test Assessment block. verify
statements evaluate
logical expressions and indicate whether the statement passes, fails, or is not tested. You
can then review the test results in the Test Manager.
Author verify
Statements
When you use verify
statements to evaluate logical expressions, the verify
statement returns a pass
, fail
, or untested
result for each time step and for the overall simulation. A fail
result at any time step results in a fail
result for the overall simulation. If there are no failing results, a pass
at any time step results in an pass
result for the overall simulation. Otherwise, the overall result is untested
.
In the Test Assessment block in sltestVerifyExample
model, the parent step uses verify
statements to compare the two local variables x
and y
during the simulation. The verify
statements in this example include optional arguments to label results in the Test Manager. For details on the verify
syntax and considerations for using it, see verify.
You can use the Test Manager to create a test case. When you run the test case, the results appear in the Verify Statements section of the test results. In this example:
verify(x >= y)
passes overall because it is true for the entire test sequence.verify
(x == y)
andverify
(x ~= y)
fail because they fail instep_1_2
andstep_1_1
, respectively.
The Test Manager displays the results:
Activate verify
Statements in the Test Assessment Block
In a When
decomposition sequence, steps activate based on a simulation condition. You can use a When
decomposition sequence in a Test Assessment block to define the simulation condition that activates a step containing a verify
statement:
If your model uses a Test Sequence block as a source, consider activating each
verify
statement using the active Test Sequence block step.If your model does not use a Test Sequence block as a source, or your test sequence steps do not correspond with the conditions to verify, activate each
verify
statement using a signal condition.
For more information on using a When
decomposition sequence, see Assess a Model by Using When Decomposition.
Activate verify
Statements by Using Test Sequence Steps
You can connect the Test Sequence and Test Assessment block with the active step signal from the Test Sequence block and activate each verify
statement with the active step. For example, the Harness1_TestSeqAndTestAssessment
harness contains a Test Sequence and Test Assessment block. The Active_Step
signal connects the blocks.
The Test Assessment block contains a When
decomposition sequence with four substeps. Each substep contains a verify
statement and activates with a different Test Sequence block step.
The Else
step in this example has no actions and handles the simulation conditions that do not match any of the preceding when
conditions. This step cannot contain a when
condition.
To activate verify
statements in a Test Assessment by using active steps in a Test Sequence block, create active step data output for the Test Sequence block. Select the Test Sequence block, and in the Property Inspector, select Create data to monitor the active step and set the Data Type to Enum
. Enter a name in Enum Name.
Then, create a data input for the Test Assessment block. Open the Test Assessment block, and, in the Symbols pane, point to Input, click Add data, and name the input. Connect the Test Sequence block output to the Test Assessment block input.
Create a When
decomposition in the Test Assessment block. By default, the Test Assessment block has a When
decomposition sequence. To change between a standard sequence and a When
decomposition sequence, right-click the parent step and select When decomposition. For each When
decomposition step, define when the step is active by using the active step enumeration data.
VerifyBoth when TSActiveStepIN == ... TSActiveStepEnum.PressBothButtons
Activate verify
Statements by Using Signal Conditions
If your model does not use a Test Sequence block as a source, or if the steps in the Test Sequence block do not correspond with the conditions to verify, you can use unique signal conditions to activate the steps containing verify
statements. Place verify
statements in a When
decomposition sequence, and use conditional statements in the When
conditions.
For example, the test harness, Harness2_AssessWithSignalInputs
uses a Signal Editor block input.
The Test Assessment block in the harness contains a When
decomposition sequence and each substep contains a verify
statement. A unique signal condition activates each substep.
See Also
Test Sequence Editor | Test Sequence | Test Assessment | verify | sltest.testmanager.Assessment
| sltest.testmanager.AssessmentSymbol
| sltest.testmanager.TestCase