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C28x-ePWM

Assign ePWM signals to GPIO pins.

The ePWM X-BAR brings signals to the ePWM modules. Specifically, the ePWM X-BAR is connected to the Digital Compare (DC) submodule of each ePWM module for actions such as tripzones and syncing. You can set the following parameters for ePWM:

EPWM clock divider (EPWMCLKDIV)

Select the ePWM clock divider. This parameter is available only for F2807x, F2837x, F2838x processors.

Select the 'EPWM clock divider (EPWMCLKDIV)' option used for CPU1

Available only for CPU2 of dual C28x core processors. Its value must be the same as the value of the parameter EPWM clock divider (EPWMCLKDIV) selected in CPU1.

TZx Input X-BAR

Indicates the trip-zone input X-BAR.

Note

This parameter appears only for specific processors.

TZx pin assignment

Assign the trip-zone input x (TZx) to a GPIO pin.

Note

  • For F2807x, F2837x, F28004x and F2838x processors the TZx pin assignment is disabled.

  • The TZ# pin assignments are available only for TI F280x processors.

TRIP# MUX select

Select the MUX to map the signal to the MUX output.

Selecting Disable all will indicate that all MUXes are disabled and the TRIP X-BAR# is not configured.

This parameter appears only for specific processors.

Select MUX input

Select the input to the MUX selected in TRIP# MUX select.

Select the input signals for the MUX which is sent to the ePWM module. You can select one signal per MUX. The input signal to the MUX varies based on the MUX selected and processor.

The following table lists the TRIP MUX select and Select MUX input for C28x processor F2838x. The row headers 0-3 represent the Select MUX input and column headers 0-31 represent the TRIP MUX select.

ePWM X-BAR Mux Configuration Table - F2838x

Select MUX INPUT 0123
TRIP# MUX select
0CMPSS1.CTRIPHCMPSS1.CTRIPH_OR_ CTRIPLADCAEVT1ECAP1.OUT
1CMPSS1.CTRIPLINPUTXBAR1CLB1_4.1ADCCEVT1
2CMPSS2.CTRIPHCMPSS2.CTRIPH_OR_ CTRIPLADCAEVT2ECAP2.OUT
3CMPSS2.CTRIPLINPUTXBAR2CLB1_5.1ADCCEVT2
4CMPSS3.CTRIPHCMPSS3.CTRIPH_OR_ CTRIPLADCAEVT3ECAP3.OUT
5CMPSS3.CTRIPLINPUTXBAR3CLB2_4.1ADCCEVT3
6CMPSS4.CTRIPHCMPSS4.CTRIPH_OR_ CTRIPLADCAEVT4ECAP4.OUT
7CMPSS4.CTRIPLINPUTXBAR4CLB2_5.1ADCCEVT4
8CMPSS5.CTRIPHCMPSS5.CTRIPH_OR_ CTRIPLADCBEVT1ECAP5.OUT
9CMPSS5.CTRIPLINPUTXBAR5CLB3_4.1ADCDEVT1
10CMPSS6.CTRIPHCMPSS6.CTRIPH_OR_ CTRIPLADCBEVT2ECAP6.OUT
11CMPSS6.CTRIPLINPUTXBAR6CLB3_5.1ADCDEVT2
12CMPSS7.CTRIPHCMPSS7.CTRIPH_OR_ CTRIPLADCBEVT3ECAP7.OUT
13CMPSS7.CTRIPLADCSOCACLB4_4.1ADCDEVT3
14CMPSS8.CTRIPHCMPSS8.CTRIPH_OR_ CTRIPLADCBEVT4EXTSYNCOUT
15CMPSS8.CTRIPLADCSOCBCLB4_5.1ADCDEVT4
16SD1FLT1.COMPHSD1FLT1.COMPH_OR_ COMPLReservedERRORSTS.ERROR
17SD1FLT1.COMPLINPUTXBAR7CLB5_4.1CPU1.CLA1HALT
18SD1FLT2.COMPHSD1FLT2.COMPH_OR_ COMPL ECATSYNC0
19SD1FLT2.COMPLINPUTXBAR8CLB5_5.1ECATSYNC1
20SD1FLT3.COMPHSD1FLT3.COMPH_OR_ COMPLReservedReserved
21SD1FLT3.COMPLINPUTXBAR9CLB6_4.1Reserved
22SD1FLT4.COMPHSD1FLT4.COMPH_OR_ COMPLReservedReserved
23SD1FLT4.COMPLINPUTXBAR10CLB6_5.1Reserved
24SD2FLT1.COMPHSD2FLT1.COMPH_OR_ COMPLReservedReserved
25SD2FLT1.COMPLINPUTXBAR11MCANA.FEVT0CLB7_4.1
26SD2FLT2.COMPHSD2FLT2.COMPH_OR_ COMPLReservedReserved
27SD2FLT2.COMPLINPUTXBAR12MCANA.FEVT1CLB7_5.1
28SD2FLT3.COMPHSD2FLT3.COMPH_OR_ COMPLReservedReserved
29SD2FLT3.COMPLINPUTXBAR13MCANA.FEVT2CLB8_4.1
30SD2FLT4.COMPHSD2FLT4.COMPH_OR_ COMPLReservedReserved
31SD2FLT4.COMPLINPUTXBAR14ReservedCLB8_5.1

ePWM X-BAR Mux Configuration Table - F28004x

Select MUX INPUT 0123
TRIP# MUX select
0CMPSS1.CTRIPHCMPSS1.CTRIPH_OR_CTRIPLADCAEVT1ECAP1OUT
1CMPSS1.CTRIPLINPUTXBAR1CLB1_OUT4ADCCEVT1
2CMPSS2.CTRIPHCMPSS2.CTRIPH_OR_CTRIPLADCAEVT2ECAP2OUT
3CMPSS2.CTRIPLINPUTXBAR2CLB1_OUT5ADCCEVT2
4CMPSS3.CTRIPHCMPSS3.CTRIPH_OR_CTRIPLADCAEVT3ECAP3OUT
5CMPSS3.CTRIPLINPUTXBAR3CLB2_OUT4ADCCEVT3
6CMPSS4.CTRIPHCMPSS4.CTRIPH_OR_CTRIPLADCAEVT4ECAP4OUT
7CMPSS4.CTRIPLINPUTXBAR4CLB2_OUT5ADCCEVT4
8CMPSS5.CTRIPHCMPSS5.CTRIPH_OR_CTRIPLADCBEVT1ECAP5OUT
9CMPSS5.CTRIPLINPUTXBAR5CLB3_OUT4Reserved
10CMPSS6.CTRIPHCMPSS6.CTRIPH_OR_CTRIPLADCBEVT2ECAP6OUT
11CMPSS6.CTRIPLINPUTXBAR6CLB3_OUT5Reserved
12CMPSS7.CTRIPHCMPSS7.CTRIPH_OR_CTRIPLADCBEVT3ECAP7OUT
13CMPSS7.CTRIPLADCSOCAOCLB4_OUT4Reserved
14ReservedReservedADCBEVT4EXTSYNCOUT
15ReservedADCSOCBOCLB4_OUT5Reserved
16SD1FLT1.COMPHSD1FLT1.COMPH_OR_COMPLReservedReserved
17SD1FLT1.COMPLINPUT7ReservedCLAHALT
18SD1FLT2.COMPHSD1FLT2.COMPH_OR_COMPLReservedReserved
19SD1FLT2.COMPLINPUT8ReservedReserved
20SD1FLT3.COMPHSD1FLT3.COMPH_OR_COMPLReservedReserved
21SD1FLT3.COMPLINPUT9ReservedReserved
22SD1FLT4.COMPHSD1FLT4.COMPH_OR_COMPLReservedReserved
23SD1FLT4.COMPLINPUT10ReservedReserved
24ReservedReservedReservedReserved
25ReservedINPUT11ReservedReserved
26ReservedReservedReservedReserved
27ReservedINPUT12ReservedReserved
28ReservedReservedReservedReserved
29ReservedINPUT13ReservedReserved
30ReservedReservedReservedReserved
31ReservedINPUT14ReservedReserved

ePWM X-BAR MUX Configuration Table - F2807x and F2837x

Select MUX INPUT 0123
TRIP# MUX select
0CMPSS1.CTRIPHCMPSS1.CTRIPH_OR_CTRIPLADCAEVT1ECAP1OUT
1CMPSS1.CTRIPLINPUTXBAR1CLB1_OUT4 ADCCEVT1
2CMPSS2.CTRIPHCMPSS2.CTRIPH_OR_CTRIPLADCAEVT2ECAP2OUT
3CMPSS2.CTRIPLINPUTXBAR2CLB1_OUT5 ADCCEVT2
4CMPSS3.CTRIPHCMPSS3.CTRIPH_OR_CTRIPLADCAEVT3ECAP3OUT
5CMPSS3.CTRIPLINPUTXBAR3CLB2_OUT4 ADCCEVT3
6CMPSS4.CTRIPHCMPSS4.CTRIPH_OR_CTRIPLADCAEVT4ECAP4OUT
7CMPSS4.CTRIPLINPUTXBAR4CLB2_OUT5 ADCCEVT4
8CMPSS5.CTRIPHCMPSS5.CTRIPH_OR_CTRIPLADCBEVT1ECAP5OUT
9CMPSS5.CTRIPLINPUTXBAR5CLB3_OUT4 ADCDEVT1
10CMPSS6.CTRIPHCMPSS6.CTRIPH_OR_CTRIPLADCBEVT2ECAP6OUT
11CMPSS6.CTRIPLINPUTXBAR6CLB3_OUT5 ADCDEVT2
12CMPSS7.CTRIPHCMPSS7.CTRIPH_OR_CTRIPLADCBEVT3
13CMPSS7.CTRIPLADCSOCAO CLB4_OUT4ADCDEVT3
14CMPSS8.CTRIPHCMPSS8.CTRIPH_OR_CTRIPLADCBEVT4EXTSYNCOUT
15CMPSS8.CTRIPLADCSOCBOCLB4_OUT5 ADCDEVT4
16SD1FLT1.COMPHSD1FLT1.COMPH_OR_COMPL Reserved Reserved
17SD1FLT1.COMPL Reserved Reserved Reserved
18SD1FLT2.COMPHSD1FLT2.COMPH_OR_COMPL Reserved Reserved
19SD1FLT2.COMPL Reserved Reserved Reserved
20SD1FLT3.COMPHSD1FLT3.COMPH_OR_COMPL Reserved Reserved
21SD1FLT3.COMPL Reserved Reserved Reserved
22SD1FLT4.COMPHSD1FLT4.COMPH_OR_COMPL Reserved Reserved
23SD1FLT4.COMPL Reserved Reserved Reserved
24SD2FLT1.COMPHSD2FLT1.COMPH_OR_COMPL Reserved Reserved
25SD2FLT1.COMPL Reserved Reserved Reserved
26SD2FLT2.COMPHSD2FLT2.COMPH_OR_COMPL Reserved Reserved
27SD2FLT2.COMPL Reserved Reserved Reserved
28SD2FLT3.COMPHSD2FLT3.COMPH_OR_COMPL Reserved Reserved
29SD2FLT3.COMPL Reserved Reserved Reserved
30SD2FLT4.COMPHSD2FLT4.COMPH_OR_COMPL Reserved Reserved
31SD2FLT4.COMPLReserved ReservedReserved

TRIP# MUX (MUX 0->31)

Indicates the input signal selected for each MUX. For example, XXXX1XXXXXXXXXXXXXXXXXXXXXXXXXX indicates that input signal 1 was selected for MUX 4. X indicates that the MUX is disabled and no signal from the MUX will be sent to the ePWM X-BAR output.

All the signals which are selected will be logically OR'd and sent to the TRIP# signal of ePWM.

This parameter appears only for specific processors.

RESET TRIP# MUX

Resets the signal selection for the MUX done so far.

Resets the TRIP# MUX (MUX 0->31) and Select MUX input inputs.

Invert TRIP# output

Enable to invert the TRIP output signal to the ePWM.

SYNCI Input X-BAR

Select the input X-BAR for SYNCI.

This parameter appears only for specific processors.

SYNCI pin assignment

Indicates the GPIO pin for the ePWM external input

For F2807x, F2837x, F28004x and F2838x processors the SYNCI pin assignment is disabled.

SYNCO pin assignment

Assign the ePWM external sync pulse output (SYNCO) to a GPIO pin.

Note

SYNCI and SYNCO pin assignments are available for TI F28044, TI F280x, TI Delfino F2833x, TI Delfino F2834x, TI Piccolo F2802x, TI Piccolo F2803x, TI Piccolo F2806 processors.

PWM#x pin assignment

Assign the GPIO pin to the PWM#x module.

GPTRIP#SEL pin assignment(GPIO0~63)

Assign the ePWM trip-zone input to a GPIO pin.

Note

The GPTRIP#SEL pin assignment is available only for TI Concerto F28M35x/F28M36x processors.

PWM1SYNCI/ GPTRIP6SEL pin assignment

Assign the ePWM sync pulse input (SYNCI) to a GPIO pin.

Note

The PWM1SYNCI/GPTRIP#SEL pin assignments are available only for TI Concerto F28M35x/F28M36x processors.

DCxHTRIPSEL (Enter Hex value between 0 and 0x6FFF) / DCBHTRIPSEL (Enter Hex value between 0 and 0x6FFF)

Assign the Digital Compare A high trip input to a GPIO pin.

Note

DCxHTRIPSel pin assignment is available only for TI Concerto F28M35x/F28M36x processors.

DCxLTRIPSEL (Enter Hex value between 0 and 0x6FFF) / DCBLTRIPSEL (Enter Hex value between 0 and 0x6FFF)

Assign the Digital Compare A low trip input to a GPIO pin.

Note

The DCxLTRIPSEL pin assignment is available only for TI Concerto F28M35x/F28M36x processors.

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