You are using Variable dimensions and the coding style is not suitable for HDL Code generation or FPGA/ASIC synthesis.
Few other observations:
There are some comms internal toolbox functions such as "comm.internal.utilities.de2biBase2RightMSB" used in the floating point code targeted for the fixed-point conversion workflow. These functions do not support fixed-point types as inputs.
function dec = bi2deOptimized(bin)
dec = comm.internal.utilities.bi2deRightMSB(bin, 2);
function bin = de2biOptimized(dec, n)
bin = comm.internal.utilities.de2biBase2RightMSB(dec, n);
You may needs to cast the inputs to double at the minimum to get through float2fixed conversion but you would be stuck in HDL code generaiton eventually; consider providing HDL friendly replacement functions with sutiable fixed-point equivalents.
You also need to manually make TimeStamp variable to 2 bits wordlength; bitshift does not support shifting 1 bit for some reason. Needs more investigation.
Please update the code to remove variable dimensions and share the attachment.