How do I generate code only with HDL Coder?

How can I generate VHDL/Verilog code only, without invoking a build in a synthesis tool?

Answer 1

[MathWorks Support Team]

To generate HDL code from your MATLAB function or Simulink model without compiling any code, select the following settings in "Workflow Advisor" tool:

• Workflow: "Generic ASIC/FPGA"
• Synthesis tool: "No synthesis tool available on system path" or "No synthesis tool specified"

From MATLAB:

From Simulink:

In a Simulink model, you have the following additional ways to generate HDL code only:

• You can use the "Generate HDL Code" button in Simulink Toolstrip, or the "Generate HDL for Subsystem" option from the HDL Coder Block context menu. See: https://www.mathworks.com/help/hdlcoder/ug/set-hdl-code-generation-options.html
• You can also use the "makehdl" command: https://www.mathworks.com/help/hdlcoder/ug/generate-hdl-code-from-simulink-model-from-command-line.html