E310/HDL Coder - How can I design a model where the ARM application individually requests frames of samples from the E310 Receiver/FPGA?

As the title states, I'm trying to start with a simple model where an ARM application (System Object) may signal the FPGA to request a single frame/vector of data. I'm working with Simulink. Streaming data by choosing AXI-Stream as the interface in the HDL Workflow Advisor is straightforward enough, but that isn't what I'm going for.

For an example, the FPGA would be configured to compute an FFT for N samples. I'd like for the ARM application to signal once to request the E310 to capture N samples, then for the FPGA to compute the FFT and then perform a transfer of the FFT back to the ARM.

It doesn't have to be these particular operations, just trying to get an idea for what the architecture/relevant blocks or calls might be.

Thanks in advance for your help!

Answer 1

[Kiran Kintali]

HW/SW Codesign workflow of SDR algorithms for USRP™ embedded series radio hardware

This guide helps you to deploy partitioned hardware-software (HW/SW) co-design implementations of SDR algorithms for USRP™ embedded series radio hardware.

You can use Simulink® to design, simulate, and verify your application, and to perform what-if scenarios to optimize performance. Then you can decide which system elements to implement on the programmable logic, and which system elements run on the ARM® processor.

Using this workflow, you can automatically generate HDL code for the programmable logic using HDL Coder™, and generate C code for the ARM processor using Embedded Coder®. Finally, you can implement the design on the radio hardware.

This workflow uses the Target a QPSK Transmitter and Receiver to a USRP E3xx using HW/SW Co-Design Workflow example as a reference design.

You can additionally review the doc page below, and explore the receiver and transmitter interrupts. One of the option used in the example ensures that the ARM and the FPGA are running in synchronization and means that the software will be driven by a schedule tick at the frame rate.

https://www.mathworks.com/help/supportpkg/usrpembeddedseriesradio/ug/system-timing.html

[Kevin Lee]

This is helpful! The system timing page is interesting, I did not know this was how things worked under the hood. I had already read through the other linked pages at other times!

However, I'll reiterate the original question to specify that I'd like for the end system as a whole to operate not on a regular schedule tick, but rather on an arbitrary (possibly asynchronous) request rate sent from the ARM. The rates specified in the user logic (FPGA) will still remain as they are, but only once the ARM sends the request signal does the user logic perform its operation on a specific number of samples at the specified sample rates and transfer it to the ARM. This would entail that samples would be dropped in between requests.

The system timing page covered interrupts which seems close, but an interrupt goes in the direction of FPGA to the ARM, when the signaling I'm after is from the ARM to the FPGA.

I also tried [edit comm.SDRRxE3xx] to see if I could modify it to capture only some number of samples when prompted, but that system object is locked as a p-file.

If this isn't possible with HDL Coder, that's also fine. I'd thought I'd ask to make sure.

[Neil MacEwen]

Hi Kevin, the simplest way I can think of that you could consider would be to do this with a register. I.e. create a register input port to your Simulink block, and then add the processing required on the FPGA to process that register - for example you could look for a rising edge on the register value, and use that to trigger your FFT.

The FFT processing would only send its output to the ARM once it has received the register write from the ARM. The ARM could be set to operating system timer mode and poll the received data.

Have a look at this example - https://www.mathworks.com/help/supportpkg/usrpembeddedseriesradio/ug/hwsw-co-design-with-axi4-stream-using-usrp-e3xx.html