HDL Workflow Advisor - Step 3.2 - "Failed Index exceeds the number of array elements. Index must not exceed 2" in hdlturnkey​.interface​.ChannelBa​sed/connec​tFrameInte​rfacePort

I am trying to run step 3.2, Generate RTL Code and IP Core, in the HDL Workflow Advisor, for a model using the Xilinx ZCU208 development board. When I try to run the step, I get the following error:

Failed Index exceeds the number of array elements. Index must not exceed 2.

Index exceeds the number of array elements. Index must not exceed 2.
Error in hdlturnkey.interface.ChannelBased/connectFrameInterfacePort
Error in hdlturnkey.interface.AXI4Stream/elaborateStreamModule
Error in hdlturnkey.interface.AXI4StreamBase/elaborate
Error in hdlturnkey.elab.BoardElaboration/elaborateInterface
Error in hdlturnkey.elab.BoardElaboration/elaborateBoard
Error in hdlturnkey.TurnkeyDriver/makehdlturnkeycore
Error in hdlturnkey.TurnkeyDriver/makehdlturnkey
Error in slhdlcoder.HDLCoder/makehdlturnkey
Error in downstream.DownstreamIntegrationDriver/runIPCoreCodeGen
Error in generateIPCore
Error in Simulink.ModelAdvisor/executeCheckCallbackFct
Error in Simulink.ModelAdvisor/run
Error in Simulink.ModelAdvisor/runCheck
Error in ModelAdvisor.Node/runTaskAdvisor

I found that the ChannelBased file is an obfuscated .p file, so cannot see what is supposed to happen at this step, what index is exceeding the value, and why it is limited to 2. Is there a log file that would help me identify the source of the issue?

My model uses the AXI4-Stream interface, with a serializer (ratio 1024) and (dummy) deserializer. "Enable frame to sample conversion" optimization is diabled, and Frame to Sample Generation is turned off for my input port. In addition to the AXI4-Stream in (1) and out (1) ports, I have ADC and DAC I/Q and valid inputs and outputs.

Answer 1

[Angela Cuadros Castiblanco]

Hello,

From your description it sounds like you are using the "legacy frame-based modeling" detailed in:

https://www.mathworks.com/help/hdlcoder/ug/model-design-for-axi4-stream-interface-generation.html#butx2jk-1_sep_bu0r_op-1

To use this modeling style, the interface IDs of the streaming interface IDs must be exactly "AXI4-Stream Slave" and "AXI4-Stream Master". In the reference design for the the Xilinx ZCU208 development board, the interface IDs of the streaming interfaces are "AXI4-Stream DMA Slave" and "AXI4-Stream DMA Master" which is the reason why the legacy frame based mode fails.

As a workaround, you can use sample-based modeling (detailed in the documentation page referenced above) by taking the serializer and deserializer out of the subsystem that you are generating code for, and then map the data and valid ports of the streaming interfaces accordingly

Hope that helps!

Angela

[Kiran Kintali]

https://www.mathworks.com/help/hdlcoder/ug/model-design-for-frame-based-IP-core-generation.html

Model Design for Frame-Based IP Core Generation

You can use the frame-to-sample optimization to generate IP cores for frame-based models. The frame-to-sample optimization maps matrices and vectors to the AXI4-Stream ports and matrices to AXI4-Stream Video interfaces, and then creates the necessary logic to handle the streamed data in the frame-based design.Frame-Based Modeling for AXI4-Stream Interfaces

If your model includes streamed data, but does not process videos, you can use the frame-to-sample optimization to generate an IP core that operates on frames of data, then map the data ports to the streaming interface. You can then translate and implement your frame-based models on pixel-based hardware. See HDL Code Generation from Frame-Based Algorithms.

When you generate the IP core, you map the frame data ports at the DUT boundary to AXI4-Stream interfaces. HDL Coder™ generates the Valid and Ready signals for each port. This image shows a top-level overview of the frame-to-sample optimization and IP core generation.

Map vectors, complex vectors, matrices, and complex matrix data to AXI4-Stream interfaces by using frame-to-sample conversion optimization. The TLAST signal is created in the generated IP core and the signal is asserted when the number of valid samples counts to the frame size of the data port.

Answer 2

[Kiran Kintali]

This is not an expected error message. Please reach out to tech support with reproduction steps.