hdl generated ip stuck at synthesis part in vivado

i have included the generated matlab hdl generated ip in my vivado block design ,but its been stuck at synthesis part,i have tried creating swamp file but it does not work ,could you please help me

Answer 1

[Kiran Kintali]

Consider using resource report to make sure you are at a high level within the limits of the FPGA resources.

sfir_fixed
makehdl('sfir_fixed/symmetric_fir', 'ResourceReport', 'on')

If the algorithm specific resource consumption is within area budgets of your target FPGA consider looking at the critical path estimation report.

>> makehdl('sfir_fixed/symmetric_fir', 'CriticalPathEstimation', 'on')

This can help provide insight into why Vivado Synthesis is not converging.

If you continue to find issues please reach to AMD/Xilinx tech support.

[Prashanthi Pathipati]

thanks for helping out sir,as you said we have to on the resourcereport i have did that in hdl workflow advisor ,in hdl code generation ,in coding style i have enabled the option generate report .