Adaptive pipelining design cannot insert the required number of registers in a feedback loop with integral modules

In my design I need to use the following design approach：

But after generating HDL code using HDLCoder, the report suggests that:

"Adaptive pipelining is not supported if the block is in a feedback loop. Number of registers required: 2; Number of registers inserted: 0.（from MATLABr21b）” and "Unable to insert required number of pipeline registers because the block, gain, is in a feedback loop and there are not enough latency budget at the output of the block. Number of registers required: 2; number of registers inserted: 0. Consider increasing the latency budget by adding more design delays in the feedback loop or using clock-rate pipelining.(from MATLABr23b）"

At the moment I don't know how to go about modifying it, I'd like to know if it's feasible for me to do so, and also how this needs to be implemented for the clock rate pipeline, I don't have the slightest clue, and I didn't understand what I should do from reading the official instructions. I hope to get the guidance of professionals, thank you very much.

If you need to provide more instructions, I am very happy to add!

Here is a screenshot of the report

Answer 1

[Kiran Kintali]

What version of MATLAB are you using? Can you please share your model?

Have you tried using Oversampling factor (>1) to allocate pipelines in the feedback loop at the clock rate?

You also need to choose a Target and Target Frequency settings.

https://www.mathworks.com/help/hdlcoder/ug/generating-a-global-oversampling-clock.html

Attaching a Sample Model.

>> hdlsaveparams('basic_ap_floop_24a/HDL DUT')
%% Set Model 'basic_ap_floop_24a' HDL parameters
hdlset_param('basic_ap_floop_24a', 'AdaptivePipelining', 'on');
hdlset_param('basic_ap_floop_24a', 'HDLSubsystem', 'basic_ap_floop_24a');
hdlset_param('basic_ap_floop_24a', 'Oversampling', 2);
hdlset_param('basic_ap_floop_24a', 'SynthesisTool', 'Xilinx Vivado');
hdlset_param('basic_ap_floop_24a', 'SynthesisToolChipFamily', 'Virtex7');
hdlset_param('basic_ap_floop_24a', 'SynthesisToolDeviceName', 'xc7v2000t');
hdlset_param('basic_ap_floop_24a', 'SynthesisToolPackageName', 'fhg1761');
hdlset_param('basic_ap_floop_24a', 'SynthesisToolSpeedValue', '-1');
hdlset_param('basic_ap_floop_24a', 'TargetFrequency', 100);

Generate code with Adaptive Pipelining; check the codegen report; see the generated model for the locaiton of the pipelines in the feedback and the additional balance delays.

>> makehdl('basic_ap_floop_24a/HDL DUT')

[智浩 刘]

Thanks，Kiran Kintali.

I use both r23b and r21b.

The model is as shown in the picture in the question(Sorry I haven't found a way to submit a model yet). I am trying to set the oversampling factor. Preliminary results show that it is possible to insert the required number of registers. However, I found that I will not be able to use the generated HDL code, mainly there is something about the use of the clk and clk_enb signals, and am learning how to use them in the FPGA.

I'm trying to generate testbench files with HDL Coder to learn how to use it, but it's not generating testbench files properly with the current setup, and I'm trying to fix it.

[Kiran Kintali]

Check the generated codegen report basic_ap_floop_24a_codegen_rpt.html

>> makehdl('basic_ap_floop_24a/HDL DUT')
### Working on the model basic_ap_floop_24a
### Generating HDL for basic_ap_floop_24a/HDL DUT
### Using the config set for model basic_ap_floop_24a for HDL code generation parameters.
### Running HDL checks on the model 'basic_ap_floop_24a'.
### Begin compilation of the model 'basic_ap_floop_24a'...
### Working on the model 'basic_ap_floop_24a'...
### Working on... GenerateModel
### Begin model generation 'gm_basic_ap_floop_24a'...
### Rendering DUT with optimization related changes (IO, Area, Pipelining)...
### Model generation complete.
### Generated model saved at hdlsrc\basic_ap_floop_24a\gm_basic_ap_floop_24a.slx
### Begin VHDL Code Generation for 'basic_ap_floop_24a'.
### MESSAGE: The design requires 2 times faster clock with respect to the base rate = 1.
### Begin VHDL Code Generation for 'HDL_DUT_tc'.
### Working on HDL_DUT_tc as hdlsrc\basic_ap_floop_24a\HDL_DUT_tc.vhd.
### Code Generation for 'HDL_DUT_tc' completed.
### Working on basic_ap_floop_24a/HDL DUT as hdlsrc\basic_ap_floop_24a\HDL_DUT.vhd.
### Code Generation for 'basic_ap_floop_24a' completed.
### Generating HTML files for code generation report at basic_ap_floop_24a_codegen_rpt.html
### Creating HDL Code Generation Check Report HDL_DUT_report.html
### HDL check for 'basic_ap_floop_24a' complete with 0 errors, 0 warnings, and 1 messages.
### HDL code generation complete.
>> 

[智浩 刘]

Thank you very much, I'll learn more.I'll try what you suggested first.