How To Approach AXI4 Master Interfaces Configuration for Custom Board Deep Learning Processor Generation

I'm quite new to this, but I'd like to generate a custom deep learning processor IP core using a specific board, the Terasic DE-1 SoC, with Deep Learning HDL Toolbox.

I've found documentation on how to create a general custom board reference (https://www.mathworks.com/help/hdlcoder/ug/define-and-register-custom-board-and-reference-design-for-intel-soc-workflow.html) and how to generate a deep learning processor IP Core (https://www.mathworks.com/help/deep-learning-hdl/ug/define-custom-board-and-reference-design-for-dl-ip-core-workflow.html), but I'm unsure about configuration of the AXI-4 interfaces. Would I even be able to do this on this particular board? Would it utilize using Quartus first to further configure something?

Answer 1

[Umar]

Hi Jacob,

To answer your question,configuring AXI-4 interfaces on a specific board typically involves defining the interface parameters and connecting them to the appropriate hardware pins. While Quartus is commonly used for FPGA design, MATLAB can also be utilized for configuring AXI-4 interfaces without the need for Quartus. Ensure that you have the necessary board support package or hardware description files to correctly configure the interfaces on your board.

Good luck with your project.