MATLAB Ethernet AXI manager frequent timeout issue

Hi,

MATLAB HDL verifier's Ethernet Axi manager times out when writing large array. I am using Ethernet on VCU118 board. When I ping from CMD, it never misses any packets. When I send smaller array in incremental burst, it never fails. But when the array size is >256, I get the following error frequnetly:

What can be the reason??? Just sending 257 numbers, it fails. 256 numbers it works!

clc
close all
clearvars
tic

fpga5ID = 5;
mem_FPGA5 = aximanager('AMD', 'interface', 'PLEthernet', ...
    'DeviceAddress', ['192.168.0.', num2str(fpga5ID)], ...
    'Port', num2str(50100 + fpga5ID));
toc

tic;
for i=1:100000
    writememory(mem_FPGA5, 0, 10*ones(1,257), 'BurstType', 'Increment');
end
toc


Elapsed time is 3.086278 seconds.
Error using aximasterudp_mex
Transaction request timed out. Check whether the target board is powered
on and connections to the board are proper.


Error in hdlverifier.AXIManagerEthernet/writememory

Error in untitled (line 15)
    writememory(mem_FPGA5, 0, 10*ones(1,257), 'BurstType', 'Increment');
    ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
>> 

[Navya Seelam]

Can you share the address mapping for your design? What is the address space of the AXI Slave connected to Ethernet AXI Manager IP?

[Nadatimuj]

Hi Navya,

Please see if this explains, thanks. Also please note, I use the same slave IP with PCIE AXI manager which never shows any errors.

[Navya Seelam]

I was not able to reproduce the issue on VCU118. I suspect the issue is with how PCS PMA IP is configured. Can you refer to https://github.com/alexforencich/verilog-ethernet to configure it correctly?

[Nadatimuj]

@Navya Yeah I talked to Alex multiple times and my designs wraps up all his configurations and then combined MATLAB SGMII IP design that was privately sent to me via Mathworks support case. If you have a working design that does not reproduce this, would you be able to share it with me? Thanks.