An instance of AMD cannot be generated in the HDL Coder

When I was in fulfilling the following url, found that the DUT can't generate AMDFloatingpointoperators verilog code.

https://ww2.mathworks.cn/help/hdlcoder/ug/generate-hdl-code-amd-floating-point-library.html

The version of matlab I'm using is R2024b. These are some configurations of my configuration parameters.

I want to know if my DUT still uses an NFP instance instead of an AMD instance. If so, then how should I set it up to generate an AMD instance on the website

[Yongsheng]

From the Command Window output you shared, the Multiply and Add blocks are mapped to NFP, as shown in lines like:

### Working on hdlcoderAMDFPAndNFP/DUT/nfp_add_single as hdl_prj/hdlsrc/hdlcoderAMDFPAndNFP/nfp_add_single.v.

The expected output for blocks mapped to AMD Floating Point Operators should look like:

### Working on hdlcoderAMDFPAndNFP/DUT/amdfp_add_single_block as hdl_prj/hdlsrc/hdlcoderAMDFPAndNFP/amdfp_add_single_block.v.

Additionally, the Floating-Point Resource Report page in the Code Generation Report shows how floating-point blocks are mapped. For example, in the following report, the Adder and Multiplier are mapped to AMD Floating Point Operators, while tanh is mapped to NFP.

MATLAB R2024b officially supports Vivado version 2023.1, as stated in the https://uk.mathworks.com/help/releases/R2024b/hdlcoder/gs/language-and-tool-version-support.html .

Please verify the Vivado version you are using.

[丰硕]

Thank you very much for your reply. At present, it seems that I am using a higher version of Vivado. Next, I will switch versions and try again

Answer 1

[Kiran Kintali]

https://www.mathworks.com/help/hdlcoder/ug/generate-hdl-code-amd-floating-point-library.html

If you are using a recent release you should be able to find this report helpful. Thsi report shows Native Floating Point or Hard Floating Point Macro usage for your operators.

Why AMD FP IP Was Not Generated?

• Based on the command window output and the code generation report, all floating-point operators in your design seem to be mapped to HDL Coder Native Floating Point (NFP).
• This fallback occurs when HDL Coder cannot successfully integrate AMD FP IP during code generation. In your case:
• You are using Vivado 2025.1 with MATLAB R2024b, but R2024b officially supports Vivado 2023.1. There could be version compatibility here. When AMD FP IP generation fails, HDL Coder automatically falls back to NFP implementation.
• We tried R2025b with 2025.1 we seen AMD FP IP is generated but output folder location has changed which could also lead to fall back to NFP as HDL Coder cannot locate the IP. We are trying to find a workaround and created an external bug report.

Do not hesitate to reach out to Tech Support for additional help.

[丰硕]

Thank you very much for your suggestion. I have already seen this window and tried to debug