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sst
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Specifying discrete sample time for variable-size signals

Asked by sst
on 13 Feb 2012
Latest activity Edited by Gilmar
on 12 Oct 2013
Hi, I am trying to use the inherit sample time setting (-1) for the Assignment block, using a variable-size signal as an index vector coming from an external source. I have selected the following options for the model:
Solver Type: Fixed Step Solver: discrete (no continuous states) Start time: 0.0 Stop Time: Inf Fixed-step size (fundamental sample time): 0.001s
When I try to update the model, I get the following error
The signal at input port 3 of '.../Assignment1' is a variable-size signal with a nondiscrete sample time. The sample time for any variable-size signal must be discrete
Even though I have specified this in the simulation configuration parameters section, why am I still getting this error message? The message goes away if I explicitly specify the sample time as 0.001 instead of -1. Any help would be greatly appreciated.
Running MATLAB R2010bSP1 on Windows XP SP3 (32-bit)
Thanks, Sundeep.

  3 Comments

TAB
2012 年 2 月 13 日
Which block is driving 'index vector' of Assignment block and what is sample time of that block?
sst
2012 年 2 月 13 日
Hello TAB, the index vector is being driven by output port 2 of a 'Find Nonzero Elements' block; the nonzero input elements themselves. The find block, in turn, is being driven by a merge block, which is configured to use variable-size signals. The sample time for the find block has been specified as -1 (inherited).
sst
2012 年 2 月 13 日
Also, the merge block has the outputs of several constant blocks as its inputs. Each constant block has the default sample time of Inf. Could that be causing the problem? Is there some way to specify programmatically that the sample time should be the same as the solver fixed-step size, for example?

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2 Answers

回答者: sst
2012 年 2 月 14 日
 採用された回答

Hi Kaustubha, while the variable-size signal was indeed a discrete sample time signal, the main input signal (In1) to the assignment block was not. By inserting a rate transition block, I was able to convert that continuous sample time signal to a discrete one, and make the error go away. My guess is that the error was pointing to that continuous signal. Thanks for your help though!

  2 Comments

sst
2012 年 2 月 14 日
At another level in the model, certain signals were indeed being identified as continuous sample time signals for some reason. These signals were being propagated to this level. Discretizing them solved the problem.
Kaustubha Govind 2012 年 2 月 15 日
Great! Thanks for posting your solution!

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回答者: Kaustubha Govind 2012 年 2 月 13 日

As TAB indicates in his/her comment, it is likely that the input signal has a continuous sample time. The Assignment block inherits that sample time (-1 means inherited sample time). The solver configuration does not affect the fact that your signal is continuous.

  5 Comments

sst
2012 年 2 月 14 日
Hi Kaustubha, the error still gets raised irrespective of the sample time I have specified for the constant blocks. It would be preferable to not have to specify the sample time explicitly. If I specify the sample time as -1, is there some sort of global sample time setting for the base simulink model that can be used anytime? Till now, I was always under the impression that the solver settings contained what we needed.
Kaustubha Govind 2012 年 2 月 14 日
If all sources specify -1 as sample-time, then I think it should indeed use the solver step-size as the sample-rate. Could you try turning on Format->Sample Time Colors. Then observe if there are any blocks with continuous sample time (black lines).
sst
2012 年 2 月 14 日
Hi Kaustubha, I did as you suggested. It looks like the variable size signal entering the assignment block is indeed a discrete sample time signal. Yet, the error I get says that the signal is a variable-size signal with a nondiscrete sample time. A bug then?

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