Problem with AXI stream interface in IP Integrator for Xilinx System generator IP cores

Hello there,

I have system generator model which I have exported as an IP core to Vivado IP integrator. I have the AXI stream interface in the model to enable the DMA in IP integrator to send a stream of data. In have verified the model for functionality in matlab environment. The simulation works fine and gives me the expected results. My problems are:

1.In address editor window of IP integrator, I don't see any address allocated to my IP core

2.When i export the model as axi-lite interface i see only zeros as output.

I want to verify whether the AXI stream intrface the way i have modeled in SysGen is correct? Where exactly am I going wrong? Can someone help me here? (I have attached design files here to give you an Idea of my problem)

[Shashi TG]

design files