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Sela
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Simulink HDL coder Shift register SIPO

Asked by Sela
on 13 Nov 2017
Latest activity Answered by David
on 18 May 2018 at 10:33

Hi everybody,

I work on model Simulink which has to generate VHDL code with the command HDL coder.

My problem is on the last step of my model.

I wish to make a shift register SIPO so with an input (1,1) and an output (1,8). My input takes new value at each clock, I would concatened all this values in one.

I have already tried with a lot of Simulink block : HDL FIFO, ShiftRegister 1 by 64, MATLAB function, bit concate... but for this instance, I have not find solution.

Could you please send me a example of ShiftRegister SIPO at 8 bits please?

Thanks for your help,

Sela

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1 Answer

Answer by David
on 18 May 2018 at 10:33

The attached is a simulink testbench for the configurable SIPO shift register.

function [update_out, po] = SIPO(update_in, si)
%#codegen
num_bits = 8; % Number of bits to output
persistent parallel_out ...
    regout ...
    count_bits % Count the bits being output
if isempty(parallel_out)
    parallel_out = fi(0,0,num_bits,0);
    regout  = fi(0,0,num_bits,0);
    count_bits = fi(0,0,ceil(log2(num_bits))+1,0);
end
po = fi(0,0,num_bits,0); % Parallel output of width "num_bits"
po(:) = regout; % Register output 
update_out = fi(0,0,1,0); % binary update output.
if update_in == 1
      % The actual shift register here.
      % join the old with the new
      % by dropping the MSB and keeping the bits below this to the LSB.
      % and appending the si input to the LSB.
      parallel_out(:) = ...
          bitconcat(... % join the following two fixed point values
          bitsliceget( parallel_out ,  num_bits-1 , 1 ) ,... get one less than MSB downto the LSB
          fi(si,0,1,0)); 
      if count_bits >= num_bits
          regout(:) = parallel_out;
          update_out = fi(1,0,1,0); % There has been an output
          count_bits(:) = 0;
      else
          count_bits(:) = count_bits + 1;
      end
end 

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