Delay Balancing Error (RTL Code/ IP Core generation)

Hallo everybody

I am using MATLAB/SIMULINK and HDL Coder to generate and IP Core for the ZedBoard DevKit.

I am encountering an issue with the "Delay Balancing" option. Basically SIMULINK got stuck during the HDL Code generation with the following error message:

“Error Delay balancing unsuccessful because Delay introduced in feedback loop cannot be path balanced. Offending Block: ....../Trigonometric Function”

1. Could someone please explain me the reason why this is happening ?

2. Could someone please explain me what should I do to avoid this situation?

I find a workaround for this issue. I have done the following changes:

- I put the "Trigonometric Fucntion" blocks into a subsystem (called "Trigonometric Fcn")

- I have disabled the "BalanceDelays" option from the HDL Coder properties

- I have set to "OFF" the "BalanceDelays" option for the "TOP" subsystem of the model

- I have left set to "Inherit" the "BalanceDelays" option for the other subsystems of the model

- but I have set to "ON" the "BalanceDelays" option for the "Trigonometric Fcn" subsystems of the model

- I have generated the "Validation Model" and I have verified that the results match the original one

This allow me to generate the HDL code and continue to the creation of the IP Core and the Vivado project.

But I would like to keep the BalanceDelays option "ON" otherwise the HDL code won't be optimised in terms of area and timing performance.

3. Could someone please give me the correct solution to this error?

I am sorry, but I cannot share the code otherwise I would attached the model and other useful information.

Thank you in advance,

Andrea Foradori

[Barry Tseng]

1. HDL Coder does not support delay balancing, if delays are introduced in a feedback loop and HDL Coder cannot balance the path delays.
2. Solution will depend on what kind of optimization you implemented on the feedback loop. For example, if you apply clock-rate pipelining inside a feedback loop, HDL Coder introduces a delay at the clock-rate, and can cause delay balancing to fail.To reduce the number of clock-rate delays, increase the Oversampling factor.

[FPGA User]

Barry, just to confirm, HDL coder will require disabling delay balancing if the model containts introduced delays inside a feeback loop.

Answer 1

[Kiran Kintali]

>> Barry, just to confirm, HDL coder will require disabling delay balancing if the model containts introduced delays inside a feeback loop.

We do not recommend turning off delay balancing. HDL Coder generates this message when BalanceDelays is set to off.

Warning'BalanceDelays' is set to 'Off' for the model. This can introduce a difference in numerics between the original model and generated model when automatic pipelines are inserted and not balanced. To verify the numerics, enable 'GenerateValidationModel', generate HDL code, and open and simulate the validation model.

You need to work towards not introduce delays in feedback loops, or manually add design delays and balance/handle delays in the loop.

If your design has a budget for OverSampling (typical control system designs have such affordance huge ratio between clock rate in MHz and data rate in KHz) set the OverSampling factor on the model and let HDLCoder use the budget to do clock rate pipelining and balance delays in feedback loops.