How to input six signals to a case statement without getting an error.

I want to input six signals to a case statement(The six signals are created using a if statement).The figure below shows the six input signals.I tried using mux, Bus creator and Vector Concatenate blocks but all of them gave dimentional errors. Is it possible to merge the six signals to one signal and how? Please let me know the best possible approach.

Answer 1

[Jonas]

I don't know exactly what you want to achieve, but I am feeling that the 'cases' block is not the best choice. You might want to look into the 'Multiport Switch' block or - if you have stateflow - the Truthtable.