Passing bus signals through a switch block

Hi

I've a model.slx which has 2 inports with 2 datatypes of equivalent child busses. These child buses are fed into a subsystem, for further processing.

I want the feed bus be switching from source inport 1 to inport 2, based on a certain condition. I'm using switch block for this.

To exlempify this:

• Bus1 and Bus2 at in1 and in2, whose child busses are selected using a busSelector.
• Bus1_child1 and Bus2_child1 are to be fed to a certain subsystem, and are inputs of a switch block (at inport 1 and 3).
• Swicth block has a condition making it switch between both busses.
• But it gives an error:

Data type mismatch. Input port 3 of 'switch_demo/Switch1' expects a signal of data type 'Bus2_child1'. However, it is driven by a signal of data type 'Bus1_child1'.
Data type mismatch. Output port 1 of 'switch_demo/From1' is a signal of data type 'Bus1_child1'. However, it is driving a signal of data type 'Bus2_child1'.
Component:Simulink | Category:Modelerror

NOTE1: This error is seen to be noticed when a non Virtual bus is being fed to swicth, if it helps identify the issue.

NOTE2: Both child busses (Bus1_child1 and Bus2_child1) have equivalent structure, except for names of child busses. Although, there is change in datatypes but i changed to while trying to resolve the error, but no luck.

So, my question will be that if the documentation says switch block can handle signals with bus DTs, then it should right ?

If the approach I've chosen to go is somewhat wrong or doesn't align with the modelling guidelines, do let me know.

Any better suggestions for switching between two equivalent busses will be more than appreciated.

Thanks!!

Umesh

Answer 1

[Mark McBroom]

Are you using Simulink Bus Objects to define the child buses? If not, try creating a Simulink.Bus object and setting the datatype of the two input ports to this bus object.

[you mess]

Yes, I already have a predefined structure/architecture of main bus and its child buses (i can see/modify it in the bus editor). Although, my current model design does not use inport. But for the sake of my own satsisfaction I did it also with the inports and got the same error.

I really can't seem to place this error.

NOTE3: when i do the same thing by making the original source/inports virtual bus then the error is not seen.

[you mess]

I'm uploading the .mat and .slx model (designed in 2016b). load and simulate the model. you'll get to know the issue.

But when the model is simulated with virtual bus, then it works without any issue.

What could you be the issue? could it be my design ?

[Mark McBroom]

You need to use the same bus type for both ports. Even though the contents of the buses are the same, you need to use the actual same bus name for both ports.

[you mess]

Well, I wasn't expecting this. I thought we can use 2 different bus datatypes in switch block. Anyway, it worked for the above attached case.

But for the real scenario which I have, it doesn't seem to work with same datatypes. I'm attaching the extended version.

NOTE4: There actually exists two buses with same attributes (Bus2_child1_def and Bus1_child1_def). And I want it to be that way, so as you said, I used only Bus1_child1_def.

Please have a look and let me know. Thanks for your help !

[Mark McBroom]

Your latest model doesn't work for the same reason. The data types for the two inputs to your subsystem are different. For Bus1.a1 and Bus2.a2, you need to make the data types the same. For example, if you change the data type of Bus2.a2 to be Bus1_child1_def, then the model works properly.

The bottom line is, for a switch block, inputs 1 and 3 must be the same data type as the switch output port.

Thanks.

mark.

[you mess]

Fair enough. Thanks for your time, if only I knew about keeping the same data type.

I'm gonna accept your answer, considering your last comment conclusive.

Thanks for the help !

Umesh