How to workaround with limitation that dpigen does not support variable sized data for Input/Output?

When using dpigen I have encountered the issue that "Variable Sized data for Input/Ouput are not supported" error. To demostrate I used the example code below:

And this is the output:

If I change line:4 to "out = filt_out(1:1:end)" the dpigen works as per normal.

Question here is we know dpigen does not support variable Input/Output, is there a good way to workaround it?

E.g. if val = 2, which means we want to select alternative index from array as final output.

[Walter Roberson]

Does it make sense for a VHDL component to have a variable-length output?

[Yufei Zhang]

@Walter RobersonThanks for the answer.

I think in HDL code we can have parameter to indicate variable length of IO port such as

module my_module #(int LENGTH, DEPTH)(

input clk,

input rst_n,

input [LENGTH-1:0] data[DEPTH]

);

//...

endmodule

The "vaiable-sized length" here may refer to a HDL parameter instead of signal value so that we will have a fixed value everytime during compile. Something like this would it be achievable in dpigen?

[Walter Roberson]

Sorry, I do not have any experience in that field.