Maximum frequency of FPGA
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Shuyi Wei on 7 Jul 2021
Answered: Sivani Pentapati on 29 Sep 2021
I am designing a PWM with Minized. When I set the fixed-step size smaller than 1e-5, the model would not run on fpga board. But the maximun frequency of Minized should be 100MHz, which means the fixed-step size could be set with 1e-8. So why couldn't I get smaller step size and how should I change the frequency of fpga in Simulink?
Sivani Pentapati on 29 Sep 2021
Based on my understanding, you want to generate HDL code for PWM. In order to run the model on fpga, the model parameters have to be configured to be compatible for HDL code generation. Please refer to the following list of model paramaters, which have to be set accordingly for code generation. The second criterion from the above link is to set the solver step size to auto, which implies that solver decides the step size, removing the option of manual assignment. Additionally, hdlsetup can also be run to set the model parameters for HDL code generation.
The target frequency of FPGA can be changed manually from HDL workflow advisor. Additionally, hdlset_param function can be used to set the target frequency from command line
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