Automatic IP core generator for Q-Learning Hardware

Version 1.1 (491 KB) by Sergio Spanò
Generator for a VHDL IP core for a Q-Learning algorithm FPGA-based hardware accelerator.
0.0
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19 Downloads
Updated 7 Jun 2022

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This app generates a VHDL IP core for a Q-Learning algorithm FPGA-based hardware accelerator. The software is compatible with all versions of the Vivado tool.

Cite As

Sergio Spanò (2026). Automatic IP core generator for Q-Learning Hardware (https://www.mathworks.com/matlabcentral/fileexchange/112745-automatic-ip-core-generator-for-q-learning-hardware), MATLAB Central File Exchange. Retrieved .

MATLAB Release Compatibility
Created with R2022a
Compatible with any release
Platform Compatibility
Windows macOS Linux
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Version Published Release Notes
1.1

Fixed system output for correct Policy Generator connection.
1.0