closed-loop-neuroengineering
This project comes from a collaboration between the Rehab Technologies Lab at the Italian Institute of Technologies (Genoa) and the MathWorks® company.
The goal is to provide a rapid-prototyping, model-based design architecture to speed up the implementation of closed-loop systems for neuroengineering application on FPGAs. This has been reached by means of the following process:
- Build a reference Simulink model to process neural data;
- Take advantage of the Fixed-Point Designer and HDL code generator provided by MathWorks to implement the model on FPGA;
- Implementation and test on commercially available systems such as the Inatn RHS Stim/Recording System (Intan website).
Fig.1 - Simulink library application example
- Custom_architecture contains all the file/scripts/models and examples to build from scratch a neuroengineering system by exploiting a model-based design approach.
- Videoguide folder which contains two tutorial videos about model design in Simulink and FPGA implementation.
For a deeper description about the repo content, please refer to: repo overview.
- Matlab R2020a
- Simulink®
- MathWorks HDL Coder™
- MathWorks Fixed-Point Designer
- Signal Processing Toolbox
- Xilinx ISE Design Suite 14.7
- If you use Windows --> Windows 10 Pro / Enterprise (required for Xilinx ISE Design Suite 14.7)
To clone this repo open your terminal and run:
git clone https://github.com/MattiaDif/closed-loop-neuroengineering
Before start, please run the installer.m script to add to your Matlab path all the project!
An explanation about how to use the repo is provided at this link: tutorial.
Backstage of the project: brief introduction of the main concepts and how the main goals have been achieved.
The Custom Architecture (CA) consists in an original Intan RHS Stim/Recording System Verilog code modification in order to hold the Verilog code generated by the Simulink model. Starting from the experience on the Simulink environment, the concept is to focus on it for the enhancement of the Intan system, in particular, taking advantage of the MathWorks HDL Coder™ which allows to convert a Simulink model in a language that can be synthetized for the FPGA.
Further details at: here.
After the modelling of the custom architecture, the next step has been its implementation on FPGA. In this step, the MathWorks HDL Coder™ is required to generate the Verilog code to be integrated into the original Verilog architecture.
Further details at: here.
To provide custom communication between the Host PC and the FPGA a personalization of the original Intan GUI has been developed. The two main modification at the C++/Qt code regards the possibility to enable or not the CA from the user interface, and adding an option to load custom parameters for the spike detection.
Further details at: here.
A custom Simulink library with ready-to-use blocks has been developed. Thus, the user can design his own algorithms for the Intan RHS system just connecting the already tested and preconfigured Simulink blocks.
Further details at: here.
You can find the closed-loop-neuroengineering documentation here: docs.
The following people have contributed to the current state of the project. Specifically:
- Development: Stefano Buccelli [1], Mattia Di Florio [1],[3], Yannick Bornat [4].
- Conceptualization/Supervision: Vijay Iyer [2], Akshay Rajhans [2], Kiran Kintali [2], Stefano Buccelli [1], Michela Chiappalone [1],[3].
For any questions, please reach via email Mattia Di Florio (di.florio.mattia@gmail.com) or Stefano Buccelli (stefano.buccelli@iit.it) or write an issue!
- Rehab Technologies IIT-INAIL Lab, Istituto Italiano di Tecnologia, Via Morego 30, 12 16163 Genova, Italy
- The MathWorks, Inc.
- Department of Informatics, Bioengineering, Robotics, System Engineering (DIBRIS), 20 University of Genova, Via all’Opera Pia 13, 16145, Genova, Italy
- Laboratoire de l’Intégration du Matériau au Système (IMS), University of Bordeaux, 18 Bordeaux INP, CNRS UMR 5218, 351 Cours de la Libération, 33405 Talence Cedex, France
For further information please refer to the scientific publication: link.
If you use this repo, please cite:
"Di Florio, M., Bornat, Y., Caré, M., Cota, V.R., Buccelli, S., & Chiappalone M. (2023, September). Enabling Model-based Design for closed-loop applications in neuroengineering. biorXiv."
Cite As
Mattia Di Florio (2024). closed-loop-neuroengineering (https://github.com/MattiaDif/closed-loop-neuroengineering/releases/tag/v0.2), GitHub. Retrieved .
M. Di Florio, Y. Bornat, M. Caré, V. R. Cota, S. Buccelli, M. Chiappalone bioRxiv 2023.09.11.557151; doi: https://doi.org/10.1101/2023.09.11.557151
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Custom_architecture/Example/CustArchitecture_Verilog/CustArchitecture
Custom_architecture/Example/CustArchitecture_input_output_check
Custom_architecture/Example_pipein/CustArchitecture_input_output_check
Custom_architecture/Simulink_lib
Custom_architecture/Source_Code
Spike_Detection_models/MultiChannelModels/Energy_Operator
Spike_Detection_models/MultiChannelModels/Sample_Thresholding
Spike_Detection_models/MultiChannelModels/Template_Matching
Spike_Detection_models/SingleChannelModels/Energy_Operator
Spike_Detection_models/SingleChannelModels/Sample_Thresholding
Spike_Detection_models/SingleChannelModels/Template_Matching
Custom_architecture/Example
Custom_architecture/Example/CustArchitecture_Verilog/CustArchitecture
Custom_architecture/Example_pipein
Custom_architecture/Simulink_lib
Custom_architecture/Source_Code
Spike_Detection_models/MultiChannelModels/Energy_Operator
Spike_Detection_models/MultiChannelModels/Sample_Thresholding
Spike_Detection_models/MultiChannelModels/Template_Matching
Spike_Detection_models/SingleChannelModels/Energy_Operator
Spike_Detection_models/SingleChannelModels/Sample_Thresholding
Spike_Detection_models/SingleChannelModels/Template_Matching
Version | Published | Release Notes | |
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0.2 |