HDL Coder Support Package for AMD FPGA and SoC Devices

Generate and deploy HDL code and Embedded Software from MATLAB and Simulink for Xilinx FPGA and SoC devices

Note: Starting in R2026b, this support package is no longer supported by MathWorks. Its functionality has been merged into SoC Blockset Support Package for AMD FPGA and SoC Devices.

HDL Coder™ enables implementation of Simulink models and MATLAB algorithms onto AMD FPGA and SoC devices for fast prototyping on hardware using the HDL Coder Support Package for AMD FPGA and SoC Devices. Using HDL Coder workflow, you can select the FPGA and SoC device, map your algorithm I/O to onboard interfaces, generate HDL IP core, and synthesize the generated code. HDL coder also provides integration with AMD tools to integrate the generated HDL IP core into the FPGA or SoC reference designs to generate bitstream that you can directly download on to the AMD FPGA or SoC devices, such as Zynq, Zynq Ultrascale+ MPSoC, Zynq Ultrascale+ RFSoC, and Versal Adaptive SoC devices. When used in combination with Embedded Coder, this solution can be utilized in a hardware/software workflow spanning simulation, C and HDL code generation, prototyping, verification, and implementation on a complete AMD SoC device.

Starting in R2024a,

• HDL Coder Support Package for Xilinx® Zynq® Platform is renamed to HDL Coder Support Package for Xilinx FPGA and SoC Devices.
• The functionality of HDL Coder Support Package for Xilinx FPGA Boards and HDL Coder Support Package for Xilinx RFSoC Devices is included in the HDL Coder Support Package for Xilinx FPGA and SoC Devices.
• You only need to install HDL Coder Support Package for Xilinx FPGA and SoC Devices to target all supported Xilinx FPGA and SoC Devices.

For specific board support, visit HDL Coder Supported Hardware