HDL Coder Evaluation Reference Guide

Getting started guide for learning and evaluating HDL Coder


Updated 6 Nov 2020

From GitHub

View License on GitHub

Editor's Note: This file was selected as MATLAB Central Pick of the Week

Guidelines for getting started using HDL Coder to generate VHDL or Verilog to target FPGA or ASIC hardware. The document provides practical guidance for:

* Setting up your MATLAB algorithm or Simulink model for HDL code generation
* How to create HDL-ready Simulink models, Stateflow charts, and MATLAB Function blocks
* Tips and advanced techniques for HDL code generation
* Code generation settings for specific FPGA/SoC targets, including AXI interfaces
* Converting to fixed-point or utilizing native floating point
* Optimizing for various goals and targets
* Verifying your generated code

It also includes examples to illustrate selected concepts.

Cite As

MathWorks HDL Coder Team (2023). HDL Coder Evaluation Reference Guide (https://github.com/mathworks/HDL-Coder-Evaluation-Reference-Guide/releases/tag/v3.0.0), GitHub. Retrieved .

MATLAB Release Compatibility
Created with R2020b
Compatible with any release
Platform Compatibility
Windows macOS Linux

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Version Published Release Notes

See release notes for this release on GitHub: https://github.com/mathworks/HDL-Coder-Evaluation-Reference-Guide/releases/tag/v3.0.0

Updated for R2018b

Japanese translation of R2017b update

Updated to R2017b

Updated Japanese version for R2016b

Updated for R2016b

Added Japanese version of the guide

To view or report issues in this GitHub add-on, visit the GitHub Repository.
To view or report issues in this GitHub add-on, visit the GitHub Repository.