Using MATLAB and FPGA-in-the-Loop to design a filter.

Version 1.0 (2.84 MB) by Pablo Trujillo Juan
Workflow to design, test, verify and implement a filter on FPGA.
5.0
(1)
214 Downloads
Updated 20 Dec 2020
View License on GitHub

This project describes the entire workflow to design a filter and implement it on an FPGA.
- Study the filter requirements.
- Design the filter using Filter Designer tool.
- Test the filter, and the quantified filter on MATLAB and Simulink.
- Generate the HDL code of the filter.
- Verify the filter on the corresponding device using FPGA-in-the-Loop
- Integrate the filter on a Vivado design and test it on the application.

Cite As

Pablo Trujillo Juan (2025). Using MATLAB and FPGA-in-the-Loop to design a filter. (https://github.com/controlpaths/line_filtering/releases/tag/1.0), GitHub. Retrieved .

MATLAB Release Compatibility
Created with R2020b
Compatible with any release
Platform Compatibility
Windows macOS Linux
Tags Add Tags

Community Treasure Hunt

Find the treasures in MATLAB Central and discover how the community can help you!

Start Hunting!

hdlsrc/untitled

hdlsrc2/untitled

hdlsrc_datacapture

hdlsrc/untitled

hdlsrc2/untitled

hdlsrc_datacapture

Version Published Release Notes
1.0

To view or report issues in this GitHub add-on, visit the GitHub Repository.
To view or report issues in this GitHub add-on, visit the GitHub Repository.