HDL cosimulation with HDL Verifier™ lets you verify that your HDL code matches your MATLAB algorithms and Simulink models by providing visibility into the HDL code. You can assess how differences between expected results and HDL simulation could affect the design at the system level.
HDL Verifier provides an HDL Cosimulation Wizard that automatically connects MATLAB and Simulink to Cadence Incisive and to Mentor Graphics ModelSim and Questa HDL simulators.
HDL Verifier exports your MATLAB algorithm or Simulink subsystem for use in functional verification environments, including those that use the Universal Verification Methodology (UVM). This approach can also be used for real number modeling of digital, analog, and mixed-signal systems. Using MATLAB Coder™, Simulink Coder™, or Embedded Coder®, HDL Verifier generates a C model with a SystemVerilog Direct Programming Interface (DPI) for behavioral simulation in your EDA simulator. This capability enables you to reuse your MATLAB algorithms and Simulink models in simulation as test sequence items, reference models, scoreboards, or system environment models. HDL Verifier also lets you customize the generated SystemVerilog component. For example, you can insert test points to observe internal signals or tune parameters in the generated SystemVerilog module at simulation time.
The supported HDL Simulators include:
HDL Verifier streamlines FPGA-in-the-loop (FIL) verification by automating the implementation of HDL code on FPGA boards connected to your MATLAB or Simulink test environment for high fidelity cosimulation in hardware. You can use this FIL technique to complement HDL cosimulation by creating a hardware prototype implementation and verifying it with your MATLAB or Simulink tests. In addition to ensuring that your MATLAB algorithm or Simulink design will behave as expected when realized in hardware, this approach can also be employed to accelerate verification of compute-intensive applications.
When used with Simulink Coder, HDL Verifier automatically generates IEEE 1666 SystemC TLM 2.0 compatible transaction-level models. Generated SystemC models have a TLM 2.0 compliant interface with a target socket that uses the TLM 2.0 generic payload. You can select options for memory mapping, processing times, and input and output buffering. HDL Verifier also generates a SystemC test bench and a report that helps you navigate the generated code.
HDL Verifier works with HDL Coder to accelerate your FPGA and ASIC design and verification workflow. When you generate HDL code for your design from HDL Coder, you can generate the interface to verify it via HDL Verifier cosimulation or FPGA-in-the-loop simulation, or you can export your test bench as a SystemVerilog DPI component to run natively in your EDA simulator.
HDL Verifier lets you integrate automatically generated code with your legacy HDL code using black-box integration. Together with HDL Coder, HDL Verifier completes the workflow for high-integrity applications that adhere to standards such as DO-254.