Jack Erickson, MathWorks
Deploying your design to an FPGA requires mapping the inputs and outputs of your design to FPGA pins, AXI registers, or other FPGA blocks. The embedded system design that the IP core generated from your design plugs is called a “reference design”. Learn how to create a reference design using Xilinx® Vivado® IP Integrator. You can also apply the same concepts to other FPGA targets. Topics include:
Select a Web Site
Choose a web site to get translated content where available and see local events and offers. Based on your location, we recommend that you select: .Select web site
You can also select a web site from the following list:
Select the China site (in Chinese or English) for best site performance. Other MathWorks country sites are not optimized for visits from your location.