Custom Reference Design, Part 2: Creating a Reference Design

Deploying your design to an FPGA requires mapping the inputs and outputs of your design to FPGA pins, AXI registers, or other FPGA blocks. The embedded system design that the IP core generated from your design plugs is called a “reference design”. Learn how to create a reference design using Xilinx^® Vivado^® IP Integrator. You can also apply the same concepts to other FPGA targets. Topics include:

• Creating a reference design project in Vivado IP Integrator
• Adding blocks to the reference design
• Creating clocking constraints
• Exporting the reference design as Tcl for use in MATLAB^®