HDL Coder

Generate VHDL and Verilog code for FPGA and ASIC designs

HDL Coder™ generates portable, synthesizable Verilog^® and VHDL^® code from MATLAB^® functions, Simulink^® models, and Stateflow^® charts. The generated HDL code can be used for FPGA programming or ASIC prototyping and design.

HDL Coder provides a workflow advisor that automates the programming of Xilinx^®, Microsemi^®, and Intel^® FPGAs. You can control HDL architecture (49:42) and implementation, highlight critical paths, and generate hardware resource utilization estimates. HDL Coder provides traceability between your Simulink model and the generated Verilog and VHDL code, enabling code verification for high-integrity applications adhering to DO-254 and other standards.

What Is HDL Coder?

HDL Code Generation

Develop and verify hardware designs at a high-level of abstraction and automatically generate synthesizable RTL code to target FPGA, ASIC, or SoC devices.

High-Level Hardware Design

Design your subsystem by choosing from over 300 HDL-ready Simulink blocks, MATLAB functions, and Stateflow charts. Simulate the hardware behavior of your design, explore alternative architectures, and generate synthesizable VHDL or Verilog.

Blocks Supported for HDL Code Generation

A Mixed-Signal Model-Based Design Flow for Automotive Sensors (25:45)

Radio Testbed Design Using HDL Coder (22:43)

Hardware Design

Add hardware architecture to algorithm design.

Hardware architecture of a pulse detection algorithm.

Vendor-Independent Targeting

Generate synthesizable RTL for use in a range of implementation workflows and FPGA, ASIC, and SoC devices. Reuse the same models for prototype and production code generation.

Accelerating Sensor Development with Rapid Prototyping and Model-Based Design

Semtech Speeds Development of Digital Receiver FPGAs and ASICs

Deploy algorithms to any FPGA, ASIC, or SoC hardware.

Generating efficient vendor-independent synthesizable RTL that can be deployed on any FPGA, ASIC, or SoC device.

Readable, Traceable HDL Code

Comply with functional safety standards such as DO-254, ISO 26262, and IEC 61508 by maintaining traceability between your requirements, model, and HDL. The generated HDL complies with industry-standard rules and is readable for code reviews.

ASIC and FPGA Workflow for ISO 26262 and IEC 61508 (3:06)

Achieving STARC and DO-254 Compliance Using HDL Coder Generated Code

Model-Based Design of Safety-Critical Avionics Systems (21:59)

The Ultra Approach To Model Based Design For Safety Critical FPGAs (23:12)

Enabling Model-Based Design for DO-254 Certification Compliance

HDL Coder generates readable synthesizable code that’s linked to the model from which it’s generated.

Generated HDL code linked to the source model and to requirements.

Predictable Design Closure

Enable algorithm and hardware design engineers to work together in a single environment, applying their individual expertise while eliminating the communication gap that exists in traditional workflows reliant on specification documents and hand-coded RTL.

Faster Hardware Development

Converge more efficiently on high-quality systems designs by integrating algorithm and hardware design in one environment. Gain insights into how hardware implementation may affect algorithm constraints early in your workflow.

Driving the Adoption of Model-Based Design for Communications System Development at Hitachi

Philips Healthcare Develops Smart Digital RF Power Subsystem for MRI Systems

Collaborate to add hardware implementation details to algorithms early in the workflow.

More Optimized Designs

Explore a wide variety of hardware architecture and fixed-point quantization options before committing to an RTL implementation. High-level synthesis optimizations efficiently map to device resources such as logic, DSPs, and RAMs.

Generate HDL Code for a Gigasamples-Per-Second (GSPS) Channelizer

Efficient Fixed-Point Implementation of a Filter on an FPGA (2:11)

Rapid Prototyping Using HDL Coder (20:51)

Designing at a high-level of abstraction enables rapid exploration of a wide range of hardware architectures and implementation options.

Rapidly explore a wide range of implementation options.

Earlier Verification

Simulate digital, analog, and software functionality at the system level early in your workflow and continuously integrate as you refine models toward implementation. Manage test suites, measure test coverage, and generate components to jumpstart RTL verification.

Improve RTL Verification by Connecting to MATLAB (41:03)

Simulink Verification, Validation, and Test

Shift-left verification to find bugs earlier when they are introduced, and generate SystemVerilog DPI-C models to start RTL verification sooner.

Verify and debug high-level functionality, and generate models for RTL verification.

FPGA, ASIC, and SoC Deployment

Deploy to prototype or production hardware. Automatically target a wide variety of devices and boards.

FPGA-Based Devices

Generate RTL that maps efficiently to Xilinx, Intel, and Microsemi FPGA and SoC devices. Map inputs and outputs to device-level I/O and AXI registers using hardware support packages for popular boards, or define your own custom reference design.

Supported FPGA Synthesis Tools and Hardware

Faster and More Accurate Control of Switched Reluctance Electric Motors Using Zynq SoC (24:20)

Deploy MATLAB Algorithms to FPGAs for Prototyping

Target FPGA prototype platforms or custom FPGA boards for production.

Testing a wireless communications algorithm on an FPGA prototype board.

ASIC Workflows

Design and verify high-level hardware functionality and architecture in context of your mixed analog, digital, and software system. Then, generate readable and rule-compliant RTL that delivers high quality-of-results (QoR) on ASIC hardware.

Faraday Accelerates SIP Development and Shrinks NAND Flash Controller ECC Engine Gate Count by 57% with Model-Based Design

Top-down FPGA and ASIC design and verification with MATLAB

Ultra-Low Power Model-Based ASIC Design for Implantable Medical Products Using HDL Coder

Real-Time Simulation and Testing

Target programmable FPGA I/O modules from Speedgoat and others using the HDL Workflow Advisor, and simulate using Simulink Real-Time™. Native floating point (9:19) HDL code generation simplifies workflows for high-accuracy prototyping.

Speedgoat FPGA I/O Board Programming and Configuration

CPU, FPGA, and I/O Solutions for Real-Time Simulation and Testing with Simulink (16:24)

Import HDL Coder Exports into NI LabVIEW FPGA

Perform real-time simulation by implementing a Simulink subsystem on a Speedgoat FPGA I/O board.

Using the HDL Workflow Advisor to target a Speedgoat FPGA I/O board.

Featured Applications

Design and generate code for signal processing and controls applications that require the performance and efficiency of custom digital hardware.

Wireless Communications

Design system-level algorithms using live or captured signals, then add hardware architecture details or reuse subsystems and blocks from Wireless HDL Toolbox™. Deploy to preconfigured software-defined radio (SDR) platforms or to custom target hardware.

From Wireless Standard to Software-Defined Radio: An FPGA Implementation of an LTE Design (41:52)

5G Algorithms/Domain Expert at Huawei: An Insider Look

Zynq SDR Support from Communications Toolbox

Xilinx RFSoC Support from HDL Coder

Design hardware implementations of 5G, LTE, WLAN, or custom wireless communications algorithms.

Implementing hardware architectures for wireless communications algorithms.

Motor and Power Control

Implement complex low-latency control systems on FPGA, ASIC, or SoC hardware while maintaining floating-point (9:19) accuracy when needed. Simulate with plant models, deploy to prototype systems, and reuse models for production deployment.

Prototyping SoC-Based Motor Controllers with MATLAB and Simulink (19:41)

3T Develops Robot Emergency Braking System with Model-Based Design

Developing Power Converter Control Software for the J-PARC Particle Accelerator

Deploy Motor Control Algorithms to FPGA – Overview (4:03)

Deploy high-speed and high-complexity motor and power control designs to FPGA or ASIC hardware.

Generate HDL from floating-point motor control algorithms.

Video and Image Processing

Generate efficient RTL from Vision HDL Toolbox™ blocks and subsystems, which model streaming hardware implementations of vision processing algorithms. Improve algorithms by modeling memory and software transaction latency with SoC Blockset™.

Vision Processing for FPGA (5 videos)

Point-Cloud Processing Using HDL Coder (20:59)

Xilinx Zynq Support from Vision HDL Toolbox

Implement efficient high-speed video and image processing hardware.

HDL-optimized video and image processing blocks.

HIL Plant Modeling

Perform real-time simulation of complex Simscape™ hardware-in-the-loop (HIL) plant models running on FPGA rapid control prototyping systems. Use the Simscape HDL Workflow Advisor to automatically program Speedgoat FPGA I/O modules.

Deploy Simscape Plant Models to Speedgoat FPGA I/O Modules

FPGA-based Hardware-in-the-Loop (HIL) Simulation for Power Electronics (49:14)

Accelerate hardware-in-the-loop (HIL) simulation with smaller timesteps by deploying plant models to Speedgoat FPGA I/O modules.

Converting a Simscape plant model to deploy on a Speedgoat FPGA I/O board.

Design and Verification Workflow

Connecting algorithm design to hardware implementation involves more than just HDL code generation. Learn the best practices (15:25) used in prototyping and production workflows.

Design for Hardware

Develop algorithms that work efficiently on streaming data. Add hardware architecture details with HDL-ready Simulink blocks, custom MATLAB Function blocks, and Stateflow charts.

Infraredx Accelerates FPGA Development on First-of-Its-Kind Intravascular Imaging System

HDL Coder Self-Guided Tutorial

Generating HDL Code from Simulink Training Class (1:31)

MATLAB to FPGA in 5 Steps

Floating-Point to Fixed-Point

Fixed-point quantization trades off numerical accuracy for implementation efficiency. Fixed-Point Designer™ helps automate and manage this process, while native floating-point (9:19) HDL code generation delivers accuracy for wide dynamic range operations.

FPGA for DSP Applications: Fixed Point Made Easy (30:45)

You Don't Always Need to Convert to Fixed Point for FPGA or ASIC Deployment

DEMCON Reduces Development Time for FPGA-Controlled Surgical Instrument

The fixed-point quantization workflow automates and assists you in converging on your most efficient implementation.

Automate fixed-point quantization, synthesize using native floating point, or use a combination of each.

Prototyping and Verification

Apply shift-left verification to eliminate bugs early and ensure that the hardware functions as required in the system context. Use HDL Verifier™ to debug FPGA prototypes directly from MATLAB and Simulink and to generate components to speed RTL verification.

Verify HDL Implementation of PID Controllers Using FPGA-in-the-Loop

Harris Accelerates Verification of Signal Processing FPGAs

Verifying the Hardware Implementation of Automotive Radar Signal Processing with MATLAB (26:55)