Generate VHDL and Verilog code for FPGA and ASIC designs
High-Level Hardware Design
Design your subsystem by choosing from over 300 HDL-ready Simulink blocks, MATLAB functions, and Stateflow charts. Simulate the hardware behavior of your design, explore alternative architectures, and generate synthesizable VHDL or Verilog.
Generate synthesizable RTL for use in a range of implementation workflows and FPGA, ASIC, and SoC devices. Reuse the same models for prototype and production code generation.
Faster Hardware Development
Converge more efficiently on high-quality systems designs by integrating algorithm and hardware design in one environment. Gain insights into how hardware implementation may affect algorithm constraints early in your workflow.
More Optimized Designs
Explore a wide variety of hardware architecture and fixed-point quantization options before committing to an RTL implementation. High-level synthesis optimizations efficiently map to device resources such as logic, DSPs, and RAMs.
Connecting algorithm design to hardware implementation involves more than just HDL code generation. Learn the best practices (15:25) used in prototyping and production workflows.
Design for Hardware
Develop algorithms that work efficiently on streaming data. Add hardware architecture details with HDL-ready Simulink blocks, custom MATLAB Function blocks, and Stateflow charts.
Prototyping and Verification
Apply shift-left verification to eliminate bugs early and ensure that the hardware functions as required in the system context. Use HDL Verifier™ to debug FPGA prototypes directly from MATLAB and Simulink and to generate components to speed RTL verification.