AMD FPGAs and Zynq SoCs

Model, verify, and program your algorithms on AMD devices

Domain experts and hardware engineers use MATLAB and Simulink to develop prototype and production applications for deployment on AMD® FPGAs, Zynq®-7000 SoCs, Zynq UltraScale+ RFSoCs/MPSoCs, and Versal® Adaptive SoCs.

With MATLAB and Simulink, you can:

  • Model hardware architecture at the system level
  • Program your FPGA or SoC without writing any code
  • Simulate and debug your FPGA or SoC using MATLAB and Simulink products
  • Generate production HDL and C code for FPGA or SoC integration

“We have a wealth of experience in our domain but little experience with FPGA integration. Simulink and HDL Coder enabled us to focus on designing intelligent algorithms for our product and not on how to run those algorithms on a specific FPGA.”

Boris Van Amerongen, Safran

Modeling and Simulation

Simulink for Model-Based Design enables you to reduce development time for AMD FPGA and Zynq SoC applications by modeling the hardware implementation at a high-level and simulating in the system context. Also, you can quantize to fixed-point (30:45) for more efficient resource usage, or generate synthesizable native floating-point (9:19) HDL to more easily program FPGAs.

HDL Coder generates synthesizable VHDL® or Verilog® directly from HDL-ready Simulink and MATLAB function blocks for applications such as signal processing, wireless communications, motor and power control, and image/video processing.

AMD System Generator for DSP and AMD Model Composer add AMD-specific blocks to Simulink for system-level simulation and hardware deployment. You can integrate System Generator blocks with native Simulink blocks for HDL code generation.

SoC Blockset lets you analyze the performance of hardware-software interaction for Zynq UltraScale+ MPSoC and RFSoC devices, including the use of memory and scheduling/OS effects.

Modeling and Simulation

Mix floating- and fixed-point operations in the same design. This trigonometric operation is implemented in floating-point using standard AMD FPGA resources.

Prototype of a wireless application running on a AMD Zynq SoC software-defined radio platform with live analysis in MATLAB and Simulink.

Prototype of a wireless application running on a AMD Zynq SoC software-defined radio platform with live analysis in MATLAB and Simulink.

Prototyping on FPGA- and Zynq SoC-Based Platforms

To get started prototyping, you can download support packages to target pre-configured AMD FPGA- and Zynq SoC-based evaluation platforms for live over-the-air software-defined radio, BLDC motor control, video and image processing with live camera input, or deep learning inference processing. HDL Coder then guides you through the steps to program your FPGA or SoC directly from Simulink without having to write HDL code. Rather than writing a Verilog testbench or a VHDL testbench, you can also verify your HDL code with MATLAB and Simulink testbenches using HDL cosimulation. Supported simulators include ModelSim™ and Questa™ from Siemens EDA, Cadence® Xcelium®, and the AMD Vivado® HDL simulator.

You can choose from multiple techniques to debug your FPGA prototype directly from MATLAB and Simulink. You can insert IP to: read or write to AXI registers (5:40) and transfer large signal or image files between MATLAB and on-board memory locations; capture data from signals internal to the FPGA for analysis in MATLAB; or test your algorithm on an evaluation kit running FPGA-in-the-loop (2:52) with your MATLAB or Simulink testbench.

HDL and IP Core Generation for Production Integration

Most blocks that support HDL code generation feature HDL block properties that let you specify custom hardware implementation options such as pipeline insertion, resource sharing, and RAM mapping. HDL code generation settings enable you to globally customize optimizations, reset styles, clock enables, naming conventions, and more. Together with the ability to design implementation architectures in Simulink you have full control over speed and area optimization for AMD FPGA and Zynq SoC devices.

You can generate readable synthesizable RTL for integration with the non-algorithmic content in Vivado®. If you install the HDL Coder support package for Zynq, then you can generate an IP core wrapper that uses various AXI protocols for communication with the Arm® processor and other device IP. You can use the Embedded Coder support package for Zynq to generate driver and application software to program the Arm application processor.

Reports from generated HDL and IP core

Reports from generated HDL and IP core. The IP Core Generation Report shows the mapping of design inputs and outputs to AXI registers and protocols.

Define a custom reference design with a placeholder with I/O mappings into which you can generate HDL.

Extending Target Platform Support

If you need to deploy to an FPGA- or SoC-based platform not included in a support package supplied by MathWorks, you can create or download a reference design and plug it into HDL Coder. You can develop the reference design using SoC Blockset or Vivado. Third-party reference designs for AMD FPGA- or SoC-based platforms are available on File Exchange from providers such as Analog Devices®, Avnet®, Speedgoat, and Trenz Electronics.