SoC Blockset
Design, evaluate, and implement SoC hardware and software architectures
SoC Blockset™ provides Simulink® blocks and visualization tools for modeling, simulating, and analyzing hardware and software architectures for ASICs, FPGAs, and systems on a chip (SoC). You can build your system architecture using memory models, bus models, and I/O models, and simulate the architecture together with the algorithms.
SoC Blockset lets you simulate memory and internal and external connectivity, as well as scheduling and OS effects, using generated test traffic or real I/O data. You can quickly explore different system architectures, estimate interface complexity for hardware and software partitioning, and evaluate software performance and hardware utilization.
SoC Blockset exports reference designs for Xilinx® and Intel® FPGA devices and SoC platforms, including Zynq®-7000, Ultrascale+™, and Intel SoC FPGAs. These reference designs can be used with Xilinx and Intel design tools.
Get Started:
Analyze Algorithm Resource Usage
Analyze Simulink models or MATLAB functions to generate reports summarizing the number of arithmetic operators required for implementation. Use these reports to compare different architectures, perform design tradeoffs, and explore hardware/software partitioning.
View the estimated number and type of operators needed to implement MATLAB functions or Simulink models.
Memory Transactions
Model and simulate shared memory transactions between hardware logic and embedded processors. Configure DMA memory controllers to arbitrate memory traffic. Account for memory latency and throughput in simulation.
Task Execution
Model task execution in an embedded process as managed by the operating system (OS). Simulate tasks with accurate timing, accounting for context switching, task preemption, and execution duration. Model software interrupts generated by FPGA fabric. Apply statistics to simulate nondeterministic task duration, or apply task durations recorded during hardware testing.
Visualize task preemption, context switching, and execution duration with timing diagrams.
SoC Model Templates
Build complete models of SoC applications from scratch using a step-by-step approach, or start from predefined templates for hardware/software coprocessing, including templates for vision and communication applications.
Build models for SoC applications using predefined model templates.
Simulation with Recorded I/O Data
Record hardware peripheral sources such as RF signals or HDMI data, and then play back recordings as sources in simulations or hardware testing.
Play back recordings as a source for simulation.
Task Execution Analysis
Simulate the software system of SoC applications by running Simulink models that incorporate timer-driven and event-driven tasks. Visualize task execution timing, preemption, rate overruns, drops, and core utilization. Replay task executions in simulation using task timing data captured from previous simulations or directly from SoC devices.
Perform statistical analysis of task execution times.
DDR Memory Performance
Analyze the memory bandwidth of system designs. Visualize simulation results and bandwidth metrics before deploying to the SoC device.
Simulate shared memory transactions and analyze performance.
On-Device Memory Performance Monitoring and Task Execution Profiling
Measure memory performance and task execution on an SoC device, and then visualize and analyze these measurements to tune an SoC model to meet your system performance requirements. Interact in real time with SoC devices from MATLAB or from your Simulink test bench.
Measure task execution with code instrumentation profiler.
Generate Embedded Software Project
When used with Embedded Coder®, SoC Blockset generates complete embedded software projects from models, including schedulers, software tasks, and I/O device driver integration.
Generate complete embedded software projects from models.
Generate Reference Designs
Generate reference designs for programmable logic. Reference designs are configured networks of IP cores with data and control paths that may be connected to external memories and software applications. SoC Blockset connects to Xilinx and Intel design tools to produce bitstreams and then programs FPGA and SoC boards.
Generate reference designs for use with HDL algorithm IP generated using HDL Coder.
Target COTS Boards and Customer Boards
Implement hardware/software applications on supported hardware kits including Xilinx Zynq UltraScale+ MPSoCs and RFSoCs, Zynq-7000 SoCs and Intel Cyclone and Arria SoC FPGAs. Target boards using hardware support packages or build support for custom boards.
Explore gallery (4 images).
Peripheral Modeling
Perform closed-loop simulations that include the behavior of peripherals such as ADCs and PWMs. Models can account for ADC-PWM synchronization and latency.
Use ADC, PWM and Task Manager blocks to model triggering behavior
Multiprocessor Architecture Modeling
Partition algorithms between multiple processors to achieve design modularity and to improve performance. Model multiprocessor execution and inter-processor data communication.
IPC Channels simulate communication between bare-metal processes executing on separate processors.
Deploy to Microcontroller and Microprocessor Boards
Perform rapid prototyping on hardware boards by generating software applications with Embedded Coder. Perform on-device profiling to fine-tune applications.
Deploy software applications to the TI Delfino F28379D LaunchPad
