Xilinx Zynq Support from HDL Coder
Generate code for the FPGA portion of the Zynq SoC
Capabilities and Features
HDL Coder Support Package for Xilinx® Zynq® Platform supports generation of IP cores that can be integrated into FPGA designs using Xilinx Vivado® Design Suite, or Xilinx ISE Design Suite.
When used in combination with Embedded Coder Support Package for Xilinx Zynq Platform, this solution can be utilized in a hardware/software workflow spanning simulation, prototyping, verification, and implementation on Xilinx Zynq devices and platforms. This makes it easier to integrate Model-Based Design into your workflow, enabling fast design iteration cycles and helping you to detect and correct design and specification errors early.
The following Xilinx evaluation boards and kits are supported:
|ZedBoard featuring the Zynq All Programmable SoC||Low-cost development board for the Xilinx Zynq All Programmable SoC|
|Xilinx Zynq All Programmable SoC ZC702 Evaluation Kit||Full-featured Zynq Evaluation Kit with a wide feature set and abundant I/O expandability. Based on the Z-7020 Zynq device.|
|Xilinx Zynq All Programmable SoC ZC706 Evaluation Kit||High-performance Zynq Evaluation Kit based on the Z-7045 Zynq device.|
|Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit||Evaluation Kit based on the Xilinx Zynq UltraScale+ EG family of devices|
|Xilinx Versal AI Core Series VCK190 Evaluation Kit||Evaluation Kit based on the Xilinx Versal AI Core Series of devices|
Custom Zynq targets can also be specified (requires MATLAB R2015a and later).
Platform and Release Support
See the hardware support package system requirements table for current and prior version, release, and platform availability.