Data Capture Workflow

Use FPGA data capture to observe signals from your design while the design is running on the FPGA. This feature captures a window of signal data from the FPGA and returns the data to MATLAB^® or Simulink^® over a JTAG or Ethernet interface.

Note

FPGA data capture over a JTAG connection is available for Intel^® and Xilinx^® FPGA boards. FPGA data capture over an Ethernet connection is available for Xilinx FPGA boards only.

You can use one of two workflows to capture data from your FPGA board and send it to MATLAB or Simulink:

HDL Coder™ Workflow — When you generate the HDL IP with HDL Coder, use the HDL Workflow Advisor tool to generate the data capture IP and integrate it in the design.
Existing HDL Design — If you have an existing HDL design, use HDL Verifier™ tools to generate the data capture IP. Then, manually integrate the generated IP into your FPGA design.

In both workflows, to capture signals from your design, HDL Verifier generates an IP core that communicates with MATLAB. Use the HDL Coder workflow to automatically integrate the data capture IP core in your design. Otherwise, manually integrate this IP core into your HDL project and deploy it to the FPGA along with the rest of your design. Then, use one of the following methods to capture data.

Capture data and send it to MATLAB – HDL Verifier generates a customized tool that returns the captured signal data. Alternatively, you can use the generated System object™ to capture data programmatically.
Capture data and send it to Simulink – HDL Verifier generates a block that has output ports corresponding to the signals you captured.

In both cases, you can specify data types for the captured data, number of windows to capture, trigger condition that controls when to capture the data, and capture condition that controls which data to capture.

When the design is running on the FPGA, first the generated IP core waits for the trigger condition that you specify. Define a trigger condition by specific values matched on one or more signals. When the trigger is detected, the logic captures the designated signals in a buffer and returns the data over the JTAG or Ethernet interface to the host machine. You can then analyze and display these signals in your MATLAB workspace or Simulink model.

To make the best use of the buffer size and capture only the valid data, you can also define a capture condition. Define a capture condition in the same way as you define the trigger condition. When both the trigger is detected and the capture condition is satisfied, the logic captures only the valid values of the designated signals.

Generate and Integrate Data Capture IP Using HDL Workflow Advisor

When you use the HDL Workflow Advisor tool to generate your HDL design, first mark interesting signals as test points in Simulink. Configure your design using the HDL Workflow Advisor tool to:

Select the type of connection channel by setting the FPGA Data Capture (HDL Verifier required) parameter in the Set Target Reference Design task. For more information, see Set Target Reference Design (HDL Coder).
Enable test point generation by selecting the Enable HDL DUT port generation for test points parameter in the Set Target Interface task. For more information, see Set Target Interface (HDL Coder).
Connect test point signals to the FPGA Data Capture interface in the Set Target Interface task.
Set up buffer size and maximum sequence depth for data collection in the Generate RTL Code and IP Core task. To include capture condition logic in the IP core, select Include capture condition logic in FPGA Data Capture. For more information, see Generate RTL Code and IP Core (HDL Coder).

Then, run through the remaining steps to generate HDL for your design and program the FPGA. The data capture IP core is integrated in the generated design. You are now ready to Capture Data.

Configure and Generate IP Core for Existing HDL Design

Before you can capture FPGA data, first specify which signals to capture and how many samples to return. Use the FPGA Data Capture Component Generator to configure these and other settings, and to generate the HDL IP core. The IP core contains:

A port for each signal you want to capture or use as part of a trigger condition
Memory to capture the number of samples you requested for each signal
JTAG or Ethernet interface logic to communicate with MATLAB
Trigger and capture condition logic that can be configured at run time
A ready-to-capture signal to control data flow from the FPGA

The tool also generates a customized FPGA Data Capture tool, System object, and model that communicate with the FPGA.

Integrate IP into FPGA

For MATLAB to communicate with the FPGA, you must integrate the generated HDL IP core into your FPGA design. If you used the HDL Workflow Advisor tool to generate your data capture IP, this step is automated. In this case, data capture IP operates on a single-clock rate, which is the primary clock of your device under test (DUT). If you did not use the HDL Workflow Advisor tool, follow the instructions in the generation report based on your device family.

Intel or Xilinx Non-Versal Devices

Follow these instructions to integrate the datacapture HDL IP core into your FPGA design that targets an Intel or a Xilinx non-Versal^® device.

Create a Quartus^® or Vivado^® project.
Navigate to the hdlsrc folder.
Follow one of these steps based on your connection type.
- JTAG — Add the generated HDL files in the hdlsrc folder to your Quartus or Vivado project. Then, instantiate the HDL IP core, datacapture, in your HDL code. Connect datacapture to the signals you requested for capture and triggers.
- Ethernet (Xilinx only) — Run the insertEthernet script by executing this command in the Vivado Tcl console.
```
source ./insertEthernet.tcl
```

Xilinx Versal Devices

Follow these instructions to integrate the datacapture HDL IP core into your FPGA design targeted on a Xilinx Versal device.

Note

FPGA data capture support for Versal devices is available for JTAG connections only.

Open your block design in Vivado.
Navigate to the hdlsrc folder.
Insert the datacapture IP into your block design and connect the IP to the BSCAN_USER2 interface of the Xilinx Versal platform CIPS IP by executing this command in the Vivado Tcl console.
```
source ./insertVersalFPGADataCaptureIP.tcl
```
To enable the BSCAN_USER2 interface, enable the PL BSCAN1 interface in the CIPS IP.
Complete the block design by connecting the clk, clk_enable, and input data ports of the data capture IP.

Compile the project and program the FPGA with the new image through a JTAG cable.

Capture Data

The FPGA data capture IP core communicates over the JTAG or Ethernet cable between your FPGA board and the host computer. Make sure that the required cable is connected. Before capturing data, you can set data types for the captured data, set trigger condition that specifies when to capture the data, and set a capture condition that specifies the data to be captured. To configure these options and capture data, you can:

Open the FPGA Data Capture tool. Set the trigger, capture condition, and data type parameters, and then capture data into the MATLAB workspace.
Use the generated System object derived from hdlverifier.FPGADataReader. Set the data types, trigger condition, and capture condition using the methods and properties of the System object, and then call the object to capture data.
In Simulink, open the generated model and configure the parameters of the FPGA Data Reader block. Then run the model to capture data.

After you capture the data and import it into the MATLAB workspace or Simulink model, you can analyze, verify, and display the data.