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Data Capture Workflow

Use the FPGA data capture feature to observe signals from your design while the design is running on the FPGA. This feature captures a window of signal data from the FPGA and returns the data to MATLAB® or Simulink®.

To use this feature, you must download a hardware support package for your FPGA board. See Download FPGA Board Support Package.

You can choose between two workflows to capture data from your FPGA board and return it to MATLAB or Simulink.

  • If you generate an HDL IP with HDL Coder™, use the HDL Workflow Advisor to generate the data capture IP and integrate it into your FPGA design.

  • If you have an existing HDL design, use HDL Verifier™ tools to generate the data capture IP. Then, manually integrate the generated IP into your FPGA design.

To capture signals from your design, HDL Verifier generates an IP core that communicates with MATLAB. Use the HDL Coder workflow to automatically integrate the data capture IP core in your design. Otherwise, manually integrate this IP core into your HDL project and deploy it to the FPGA along with the rest of your design. Then, use one of these methods to capture data.

  • For capturing data to MATLAB – HDL Verifier generates a customized app that returns the captured signal data. Alternatively, you can use the generated System object™ to capture data programmatically.

  • For capturing data to Simulink – HDL Verifier generates a block that has output ports corresponding to the signals you captured.

In both cases, you can specify data types for the captured data, number of windows to capture, and trigger conditions that control when the data is sampled.

When the design is running on the FPGA, first the generated IP core waits for the trigger condition that you specify. Define a trigger condition by specifying values matched on one or more signals. When the trigger is detected, the logic captures the designated signals to a buffer and returns the data over the JTAG interface to the host machine. You can then analyze and display these signals in your MATLAB workspace or Simulink model.

Generate and Integrate Data Capture IP Using HDL Workflow Advisor

When you use HDL Workflow Advisor to generate your HDL design, first mark desired signals as Configure Signals as Test Points (Simulink) in Simulink. Configure your design using HDL Workflow Advisor to:

  • Enable test point generation by selecting the Enable HDL DUT port generation for test points option in the Set Target Interface step. For more information, see Set Target Interface (HDL Coder).

  • Connect test point signals to the FPGA Data Capture - JTAG interface in the Set Target Interface step.

  • Set up the buffer size and maximum sequence depth for data collection in the Generate RTL Code and IP Core step. For more information, see Generate RTL Code and IP Core (HDL Coder).

Then, execute the remaining steps to generate HDL for your design and program the FPGA. The data capture IP core is integrated into the generated FPGA design. You can now Capture Data from the FPGA.

For an example of using data capture with HDL Workflow Advisor, see Debug IP Core Using FPGA Data Capture (HDL Coder).

Configure and Generate IP Core for an Existing HDL Design

Before capturing FPGA data, you must first specify which signals to capture and how many data samples to return. When using an existing HDL design, use the FPGA Data Capture Component Generator app to configure settings and generate the data capture IP core. The IP core contains:

  • A port for each signal you want to capture or use as part of a trigger condition

  • Memory to capture the number of samples you requested for each signal

  • JTAG interface logic to communicate with MATLAB

  • Trigger logic that can be configured at run time

The app also generates a customized FPGA Data Capture app, System object, and model that communicate with the FPGA.

Integrate IP into FPGA

For MATLAB to communicate with the FPGA, you must integrate the generated HDL IP core into your FPGA design. If you used HDL Workflow Advisor to generate your data capture IP, this step is automated, and the data capture IP operates on a single-clock rate, which is the primary clock of your design under test (DUT). Otherwise, follow the instructions in the generation report. Add the generated HDL files from the hdlsrc folder into your FPGA project. Then, instantiate the HDL IP core, datacapture, in your HDL code, and connect it to the signals you requested for capture and triggers. Compile the project and program the FPGA with the new image. You can now Capture Data from the FPGA.

Capture Data

The FPGA data capture IP core communicates over the JTAG cable between your FPGA board and the host computer. Make sure that the cable is connected. Before capturing data, you can set data types for the captured data, and set trigger conditions that specify when to capture the data. To configure these options and capture data, you can:

  • Open the FPGA Data Capture app. Set trigger and data type parameters, and then capture data into the MATLAB workspace.

  • Use the generated System object derived from hdlverifier.FPGADataReader. Set the data types and trigger condition using the methods and properties of the System object, and then call the object to capture data.

  • In Simulink, open the generated model, and configure the parameters of the FPGA Data Reader block. Then, run the model to capture data.

After you capture the data into the MATLAB workspace or Simulink model, you can analyze, verify, and display the data.

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