Deploying your design to an FPGA requires mapping the inputs and outputs of your design to FPGA pins, AXI registers, or other FPGA blocks. After the reference design information has been created and registered with MATLAB^®, you can generate RTL code and an IP core for your subsystem to plug into the reference design. Learn how to do so by:

• Setting up your MATLAB search path
• Using this reference design and board in the HDL Coder™ IP core generation workflow
• Generating HDL to target the reference design
• Integrating the IP core into the reference design using the reports and files created