Jack Erickson, MathWorks
Deploying your design to an FPGA requires mapping the inputs and outputs of your design to FPGA pins, AXI registers, or other FPGA blocks. After the reference design information has been created and registered with MATLAB®, you can generate RTL code and an IP core for your subsystem to plug into the reference design. Learn how to do so by:
Featured Product
Select a Web Site
Choose a web site to get translated content where available and see local events and offers. Based on your location, we recommend that you select: .
Select web siteYou can also select a web site from the following list:
Select the China site (in Chinese or English) for best site performance. Other MathWorks country sites are not optimized for visits from your location.