Jack Erickson, MathWorks
Designing deep learning, computer vision, and signal processing applications and deploying them to FPGAs, GPUs, and CPU platforms like Xilinx Zynq™ or NVIDIA® Jetson or ARM® processors is challenging because of resource constraints inherent in embedded devices. This talk walks you through a MATLAB® based deployment workflow that generates C/C++ or CUDA® or VHDL code.
For system designers looking to integrate deep learning into their FPGA-based applications, the talk helps teach the challenges and considerations for deploying to FPGA hardware, and details the workflow in MATLAB. We will briefly show how to explore and prototype trained networks on FPGAs using prebuilt bistreams from MATLAB. You can further customize your network to meet your performance requirments and hardware resource usage, generate HDL, and integrate it into an FPGA-based edge inference system.
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