High-Speed Radar and 5G NR GSPS Processing on FPGAs and SoCs
Advances in analog-to-digital converters (ADCs) have led to the development of new DSP algorithms that require frame-based processing of the incoming high-speed data for applications, such as 5G NR, radar, and signal intelligence. Hardware engineers must implement the DSP algorithms, ensuring the FPGA clock speed, resource usage, throughput rate, and power meet required specifications. Using DSP HDL Toolbox™ capabilities to implement a DDC algorithm in gigasample-per-second throughput rate on a Xilinx® UltraScale+ RFSoC board, learn how:
- Engineers can model, explore, and simulate hardware architecture options for DSP algorithms.
- Inbuilt block parameters enable implementation for sample- and frame-based processing.
- Hardware design implementation can be explored in terms of latency, throughput, and resource usage.
- Using HDL Coder capabilities can generate readable, synthesizable code in VHDL and Verilog.
You can also select a web site from the following list:
How to Get Best Site Performance
Select the China site (in Chinese or English) for best site performance. Other MathWorks country sites are not optimized for visits from your location.