Search results: tag:"fpga" - MATLAB Answers

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Results for tag:"fpga" (287 results)

Results 51 - 100 of 287

1

answer

0 votes
5 views

Discreate Integration in HDL coder for FPGA

Asked by Sanjay Kakodia on 11 May 2023

Latest activity Answered by Daichi on 18 May 2023

Accepted Answer by Daichi

Code Generation HDL Coder

0

answers

0 votes
3 views

Bitstream Generated through HDL workflow advisor

Asked by Rimsha Javed on 16 May 2023

Latest activity Edited by Rimsha Javed on 16 May 2023

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
0 views

DSP Builder HDL Import Design Example error

Asked by Finees on 15 May 2023

Latest activity Edited by Kiran Kintali on 15 May 2023

Signal Processing DSP System Toolbox Code Generation HDL Code Generation

1

answer

0 votes
3 views

HDL Coder, Assertion failed: B:\matlab\src\cgir_hdl\dom_pir_core\dutinfo.cpp:101:portIdx < m_inportMap.size()

Asked by Yeung Pok Nga on 11 May 2023

Latest activity Commented on by Yeung Pok Nga on 12 May 2023

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
1 view

How to Streaming Live Video using cudaMallocHost /cudamalloc Python/C++ via PCIe (Transmit/Receive )?

Asked by Selva Karna on 14 Oct 2022

Latest activity Answered by Ramakrishna Mandalapu on 5 Apr 2023

FPGA, ASIC, and SoC Development Vision HDL Toolbox Video Formats and Interfaces

2

answers

0 votes
11 views

Device arm_dap_0 is not programmable with FPGA in the loop tutorial.

Asked by Eduardo Flores on 29 Nov 2020

Latest activity Commented on by Walter Bomela on 31 Mar 2023

Accepted Answer by Aman Vyas

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
3 views

8bit Input UART to Stateflow Chart

Asked by Akef on 9 Mar 2023

Latest activity Answered by Naren on 29 Mar 2023

Simulink Applications Complex Logic

1

answer

0 votes
3 views

HDL Coder Not Support Strings (smoothdata)

Asked by John Brooks on 25 Mar 2023

Latest activity Commented on by John Brooks on 26 Mar 2023

Accepted Answer by Jack

Code Generation

0

answers

0 votes
1 view

Simulink automatically generates Verilog. How should it run on FPGA

Asked by wang on 21 Mar 2023

Latest activity Edited by wang on 21 Mar 2023

FPGA, ASIC, and SoC Development SoC Blockset System on Chip (SoC)

2

answers

0 votes
1 view

Matlab HDL coder error: reptmat is not supported, but in the documentation it is.

Asked by János Csanád on 2 Mar 2023

Latest activity Commented on by Ryan Baird on 6 Mar 2023

FPGA, ASIC, and SoC Development Vision HDL Toolbox HDL Code Generation and Deployment

1

answer

0 votes
0 views

Deep Learning HDL Toolbox - HDL generation

Asked by sdsd sdsd on 4 Mar 2023

Latest activity Answered by Kiran Kintali on 5 Mar 2023

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

2

answers

0 votes
7 views

Is it possible to use different target hardware for implementing deep learning HDL toolbox?

Asked by Muhammad Ihsan Al Hafiz on 20 Jan 2023

Latest activity Answered by Kiran Kintali on 24 Jan 2023

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

2

answers

0 votes
1 view

Error while targeting FPGA through simulink, I am trying to implement 'OFDM Transmit and Receive Using Analog Devices AD9361/AD9364' example of MATLAB.

Asked by Vedansh Garg on 23 Dec 2022

Latest activity Answered by Avinash on 11 Jan 2023

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
133 views

I am getting the error: make command return an error of 2, while trying to implement a software interface model of OFDM Transmit and Receive Using Analog Devices AD9361/AD9364

Asked by Vedansh Garg on 16 Dec 2022

Latest activity Answered by Harshit Gupta on 21 Dec 2022

Accepted Answer by Harshit Gupta

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
6 views

Error receiving data from RF card (FMCOMMS3), Libiio installation directory not found

Asked by Ariana Reyes on 26 Aug 2021

Latest activity Commented on by ChrisSmith on 20 Dec 2022

Wireless Communications Communications Toolbox

1

answer

0 votes
5 views

Interfacing hardware components with fixed bit width in Simulink/HDL Coder

Asked by Eirik Nordeng on 21 Nov 2022

Latest activity Edited by Andy Bartlett on 22 Nov 2022

Accepted Answer by Andy Bartlett

Simulink Simulink Environment Fundamentals Block Libraries Logic and Bit Operations

1

answer

0 votes
1 view

Can't generate .bit nor .sof file with FIL Wizard on Ubuntu.

Asked by Eduardo Flores on 27 Dec 2020

Latest activity Answered by YP on 21 Nov 2022

FPGA, ASIC, and SoC Development

1

answer

0 votes
0 views

Synthesis keeps on running for indefinite time on Xilinx RFSOC ZCU111

Asked by Abhay Sah on 19 Sep 2022

Latest activity Answered by Kiran Kintali on 6 Oct 2022

FPGA, ASIC, and SoC Development SoC Blockset SoC Blockset Supported Hardware Xilinx Devices Hardware I/O Devices

1

answer

0 votes
0 views

HDL System Blockset FPGA design generation Error

Asked by Shady on 4 Aug 2022

Latest activity Commented on by Shady on 15 Sep 2022

Accepted Answer by Chandra Adusumalli

FPGA, ASIC, and SoC Development

1

answer

0 votes
6 views

LSTM network implemention on FPGA

Asked by Sami Foery on 22 Sep 2021

Latest activity Commented on by Donald Baltus on 5 Sep 2022

Accepted Answer by Donald Baltus

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
6 views

I2C Master block in SOC FPGA

Asked by Cau Tran on 22 Aug 2022

Latest activity Commented on by Cau Tran on 30 Aug 2022

Accepted Answer by Kiran Kintali

FPGA, ASIC, and SoC Development SoC Blockset System on Chip (SoC)

0

answers

0 votes
0 views

Connecting two ZYNQ706using single MATLAB window

Asked by muhammad ahmad on 23 Aug 2022

Latest activity Commented on by muhammad ahmad on 26 Aug 2022

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
1 view

How to access HDL coder in Matlab trial version for college use ?

Asked by Aldrin Rebellow on 13 Apr 2022

Latest activity Answered by Kiran Kintali on 25 Aug 2022

Code Generation HDL Coder

2

answers

0 votes
4 views

PMSM is programed in FPGA using HDL coder.

Asked by Cau Tran on 10 Jun 2022

Latest activity Commented on by Cau Tran on 1 Aug 2022

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Code Generation from Simulink Model and Architecture Design Simscape Hardware-in-the-Loop Workflow

1

answer

0 votes
4 views

Problem with zcu111 board and Soc Builder

Asked by Luca Di Nunzio on 26 Nov 2021

Latest activity Commented on by Peyton on 20 Jul 2022

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
26 views

Which versions of Xilinx Vivado are supported with which release of HDL Workflow Advisor?

Asked by Onur Dikilitas on 27 Jun 2022

Latest activity Answered by Kiran Kintali on 29 Jun 2022

Code Generation HDL Coder Get Started with HDL Coder

1

answer

0 votes
0 views

Difference in the output of CIC decimator while using with unbuffer and without unbuffer

Asked by muhammad ahmad on 10 Jun 2022

Latest activity Commented on by muhammad ahmad on 15 Jun 2022

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

2

answers

0 votes
0 views

How do I generate HDL Code for my model that has frame based communication in Simulink HDL Coder 2.1 (R2011a)?

Asked by MathWorks Support Team on 20 Jul 2011

Latest activity Answered by Bharath Venkataraman on 9 Jun 2022

Accepted Answer by MathWorks Support Team

Code Generation

1

answer

0 votes
0 views

How to add a custom parameter in the generated module with HDL Coder,simulink?

Asked by SHIYU SONG on 9 Mar 2022

Latest activity Answered by Kiran Kintali on 17 Mar 2022

Accepted Answer by Kiran Kintali

Code Generation

1

answer

0 votes
0 views

Dose HDL coder generate Verilog HDL-1995 verision or Verilog HDL-2001 version？

Asked by Conglin Pan on 15 Mar 2022

Latest activity Answered by Bharath Venkataraman on 15 Mar 2022

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
8 views

how to implement HDL coder "clock enable"

Asked by Lennert Es on 8 Oct 2019

Latest activity Commented on by SHIYU SONG on 10 Mar 2022

Code Generation HDL Coder HDL Code Generation from Simulink Speed and Area Optimization Speed Optimization

1

answer

0 votes
1 view

Full Precision option in Fixed-Point Converter MATLAB

Asked by Joshua Ford on 28 Feb 2022

Latest activity Answered by Walter Roberson on 28 Feb 2022

Code Generation HDL Coder HDL Code Generation from MATLAB Fixed-Point Conversion Fixed Point Conversion Basics and Type Specification

1

answer

0 votes
2 views

SIMPLE HDL code generation example

Asked by Robert on 6 Feb 2022

Latest activity Edited by Kiran Kintali on 6 Feb 2022

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

1 vote
7 views

Problem with Windows Management Instrumentation while compiling a DSpace program with a FPGA card (RTI Build Error)

Asked by Raphael Romany on 25 Jan 2021

Latest activity Answered by Stefanie Schwarz on 5 Jan 2022

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
6 views

HDL Code Generation (Verilog) for a 2-D Lookup Table

Asked by VIGNESH KUMAR R C on 30 Dec 2021

Latest activity Commented on by Joel Van Sickel on 3 Jan 2022

Code Generation

1

answer

2 votes
7 views

Matlab AXI master import hdlverifier::*;does not work

Asked by Nadatimuj on 14 Feb 2021

Latest activity Commented on by Xin on 30 Dec 2021

Code Generation

1

answer

0 votes
0 views

How to build a model that is efficient for HDL conversion?

Asked by Hossein JavidHosseini on 8 Aug 2018

Latest activity Answered by Kiran Kintali on 20 Dec 2021

Code Generation HDL Coder HDL Code Generation from Simulink Speed and Area Optimization Speed Optimization

1

answer

0 votes
8 views

Where i find the registration board files for the ZC706 and FMCOMMS 2/3/4

Asked by George Lucian Chiriac on 16 Dec 2021

Latest activity Answered by Jayadhar Alla on 17 Dec 2021

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

1 vote
2 views

error in dlhdl.buildProcessor(hPCNew) step

Asked by Shaw on 7 Nov 2021

Latest activity Commented on by Shaw on 25 Nov 2021

AI, Data Science, and Statistics Deep Learning Toolbox Image Data Workflows

1

answer

0 votes
6 views

How to change frequency of sine wave on FPGA IO334?

Asked by Mitali Murkar on 30 Sep 2021

Latest activity Commented on by Mitali Murkar on 23 Nov 2021

Code Generation HDL Coder HDL Code Generation from Simulink Speed and Area Optimization Speed Optimization

0

answers

0 votes
1 view

using hw.deploy for xilinx

Asked by Shaw on 3 Nov 2021

Latest activity Commented on by JT Ferrara on 16 Nov 2021

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

3

answers

0 votes
3 views

Multiple outputs from HDL block in simulink

Asked by muhammad ahmad on 29 Oct 2021

Latest activity Commented on by JT Ferrara on 2 Nov 2021

Accepted Answer by JT Ferrara

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
0 views

using the HDL workflow advisor for a single registration target which need to include two or more matlab users IP CORES

Asked by Raz Elimelech on 19 Oct 2021

Latest activity Edited by Wang Chen on 31 Oct 2021

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
0 views

Activation Network Connection Failed in Hardware Setup

Asked by Vasanthi S on 19 Oct 2021

Latest activity Answered by Kiran Kintali on 31 Oct 2021

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
2 views

Receiving junk data using zc706 and fmcomms3 with QPSK example

Asked by karthik sharma on 5 Oct 2021

Latest activity Commented on by karthik sharma on 14 Oct 2021

Wireless Communications Communications Toolbox

2

answers

0 votes
2 views

Setup : FPGA in LOOP

Asked by Sankarshan Durgaprasad on 22 Jan 2021

Latest activity Answered by Stefanie Schwarz on 8 Oct 2021

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
1 view

I want an old Matlab Webinar on GPS Receiver

Asked by Varun Khandelwal on 1 Oct 2021

Latest activity Answered by Steven Lord on 1 Oct 2021

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
0 views

Fully Deploy CNN on ZC706 Board?

Asked by Dylan Tocci on 4 Aug 2021

Latest activity Answered by Sivani Pentapati on 1 Oct 2021

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
3 views

Maximum frequency of FPGA

Asked by Shuyi Wei on 7 Jul 2021

Latest activity Answered by Sivani Pentapati on 29 Sep 2021

FPGA, ASIC, and SoC Development

0

answers

0 votes
0 views

How to run an example "LTE MIB Recovery" without a mistake

Asked by Hutin Puy on 22 Sep 2021

Latest activity Commented on by John O'Sullivan on 22 Sep 2021

FPGA, ASIC, and SoC Development Wireless HDL Toolbox HDL-Optimized System Design

Results 51 - 100 of 287