Can't generate .bit nor .sof file with FIL Wizard on Ubuntu.

After compiling an FPGA in the loop simulink model with VHDL Verifier for Xilinx or Altera devices the new model with the FIL object appears. On windows, a new terminal shows that a new bitstream is being generated but on Ubuntu 18.05, no file is ever created. Am i missing a configuration step?

[Cau Tran]

I also had this problem. Can anyone give me advice for this one?

FIL does not generate the bitstream file.

Answer 1

[YP]

Can you check if xterm is installed?

FYI https://www.mathworks.com/help/hdlverifier/ug/troubleshooting-fil.html