Rambus Develops DSP Blocks for ASICs Using High-Level Synthesis with HDL Coder
“Usually, verification and back-end teams cannot start integration until the first version of the spec-based RTL is ready, which may still have bugs. With this workflow based in HDL Coder, HDL can be generated from a system-level verified model with a click of a button—saving months—and guaranteeing a high-quality starting point for these teams.”
Key Outcomes
- The design process was sped up from one year to three months, and productivity increased using HDL code generation with 80% of generated code retained in the final implementation
- Verification environment development started with the auto-generated RTL code, proceeding in parallel with custom RTL development
- Moving between design generations or implementations of the same generation required limited changes to the HDL-ready Simulink model
Workflow for the DSP ASIC using HDL code generation with RTL verification and customization.
Today’s communication devices incorporate complex signal processing algorithms implemented in application-specific integrated circuits (ASICs) for higher performance, reduced end-product cost, and lower power consumption. The physical implementation process for ASICs is long. It begins before RTL verification is complete and requires manual integration of optimized adders and multipliers as well as RTL debug and observability features.
Ehud Nir, director of digital engineering at Rambus, needed to develop the DSP for a Gen6 PCIe PHY with limited time and engineering resources. A previous project for a comparable design had involved one ASIC designer writing RTL code and one verification engineer developing testbenches working for 12 months. Since the system architect had used MATLAB® and Simulink® to model the complete Gen6 serializer/deserializer (SerDes) including the DSP, Ehud decided to try speeding up the design process by using HDL Coder™ to generate an RTL reference for the ASIC implementation directly from the Simulink model.
To start, the system architect converted the floating-point Simulink model of the SerDes DSP to fixed-point. After ensuring that this model met the target electrical specifications and characteristics, an ASIC digital designer generated RTL code from the fixed-point model using HDL Coder. This reference model was regenerated from Simulink several times during the design process due to evolving requirements, such as modifications to the digital front-end filter.
The RTL code generated by HDL Coder served as a reference point for the verification team to start IP-level verification and the back-end teams to commence physical design. In the meantime, the digital designer customized the RTL code by developing the combinatorial and sequential logic to reduce power consumption and add low-power modes. Using the generated RTL as a reference enabled a complete hierarchical comparison between the customized RTL and the generated RTL reference. With added assertions, the custom RTL could be checked using HDL simulators to ensure it was bit-cycle–accurate to the reference model. As a result, a single engineer was able to produce a fully verified, timing-clean DSP netlist in less than three months, as compared to two engineers working for 12 months on the earlier project. The Gen6 PHY ASIC test chip powered by this DSP was validated in the lab with a first-pass success.
