Renesas Designs and Implements Image Processing IP Core for ASICs with Model-Based Design
- Multiple design optimizations and alternatives explored
- Efficient HDL code generated
- Vital engineering skills quickly acquired
A design and application technology company of Renesas Electronics, Renesas System Design develops ASICs, large-scale integration (LSI) systems, and microcomputers, as well as core technologies for electronics products. Among these core technologies are the advanced image processing and filtering algorithms used in automotive display systems and digital imaging equipment.
To accelerate the design and implementation of image processing intellectual property (IP) core for ASICs, Renesas engineers adopted Model-Based Design with MATLAB® and Simulink®.
“Because the IP core we develop will be used in multiple products, it must be both high-quality and flexible,” says Mamoru Kamiya, senior design engineer at Renesas system Design Company. “Model-Based Design enabled us to achieve these goals by producing a real-time prototype in the early stages of development, systematically exploring design alternatives, and building confidence in our design via extensive simulation of test cases.”
Renesas engineers wrote a floating-point version of their algorithm in C. To convert the floating-point code to fixed point, Renesas relied on a few experienced engineers who understood the algorithms and were familiar with register transfer level (RTL) hardware design. Reliance on a small number of engineers for time-consuming yet vital tasks caused project bottlenecks. HDL code was written by hand based on the fixed-point C code, causing additional delay.
Renesas needed a development approach that would enable them to complete real-time verification of their algorithms early in development. They also sought to minimize bottlenecks associated with converting from floating point to fixed point and with writing HDL code.
Renesas engineers adopted Model-Based Design for image processing algorithm development and implementation.
Working in MATLAB and Simulink, the engineers developed a floating-point model of the image processing system based on the specification. They performed early functional verification of the model by visualizing the effect of the image processing algorithm using output images produced via simulation.
The team used Computer Vision Toolbox™ to visualize output images from the system model.
With Fixed-Point Designer™, they converted the floating-point design to fixed point. The Fixed-Point Advisor tool in Fixed-Point Designer enabled them to automate steps in the conversion and to detect overflow and underflow conditions.
After comparing simulation results from the fixed-point and floating-point versions, the team used HDL Coder™ to generate synthesizable HDL code from their optimized Simulink model.
Using HDL Coder and HDL Verifier™, the team generated a test bench, which they used to verify the HDL via cosimulation with Simulink and Cadence® Incisive®.
They optimized the design for speed and area to meet the specification using a MATLAB script. This script generates multiple versions of the code using a range of HDL Coder resource sharing factors and pipelining options and synthesizes each version of the code with Synopsys® Design Compiler. The team then compared the synthesis results to identify the optimal design.
They deployed the synthesized code to a Stratix® FPGA from Altera (now part of Intel) for prototype testing, and then synthesized the IP core for ASICs with HDL code that was generated from the same Simulink model.
Renesas engineers have completed development of the image processing system using Simulink and HDL Coder, and plan to use Model-Based Design on future image processing technology projects.
Multiple design optimizations and alternatives explored. “With Model-Based Design we were able to optimize the design systematically, by changing bit widths, resource sharing factors, and the number of pipeline registers, and then regenerating HDL code,” says Kamiya. “This capability made it easy to explore alternative design options and perform parameter optimization to meet the specification.”
Efficient HDL code generated. “After optimizations, the automatically generated code had essentially the same area and speed characteristics as our best handwritten code,” says Kamiya. “The HDL code generated by HDL Coder used slightly fewer gates at target clock frequencies of 120 MHz and 275 MHz than equivalent HDL code that we had written by hand.”
Vital engineering skills quickly acquired. “By using Simulink and HDL Coder, an engineer who had no previous hardware experience learned RTL design in about six months,” says Kamiya. “This capability was instrumental in enabling a team of just three engineers to design and deploy a complex image processing algorithm on an FPGA in that same time frame.”