UVM Verification

What Is UVM Verification?

Universal Verification Methodology (UVM) verification is a standardized form of design verification used in FPGA and ASIC design projects. The development of UVM was facilitated by the Accellera Initiative, an organization that promotes standards within the electronic design automation (EDA) community, and was based on ASIC verification methodologies developed in previous years by prominent companies in the EDA industry.

The main goal of UVM verification is to improve design verification efficiency with reusable verification components. However, manually creating and debugging UVM verification components can still require a significant amount of effort, especially for new algorithmic content, and the complexity of UVM verification can be an obstacle to its adoption by design teams.

Since many algorithms developed for ASIC and FPGA design projects begin as MATLAB® code or Simulink® models, design teams can reduce testbench development efforts by generating UVM verification components directly from the MATLAB or Simulink source. With the ASIC Testbench for HDL Verifier add-on, you can automatically generate SystemVerilog DPI components from MATLAB code or Simulink models for UVM verification. These components can be used as golden reference checker models in a UVM verification scoreboard, as behavioral digital or analog component models in mixed-signal simulation, or as sequences that serve as a UVM verification stimulus.

The ASIC Testbench add-on can generate complete UVM verification environments directly from Simulink models. HDL Verifier generates SystemVerilog UVM sequence, driver, monitor, and scoreboard components from models of testbenches. It also produces SystemVerilog files for a behavioral design under test (DUT). The behavioral DUT can then be replaced with manually coded RTL or with RTL generated using HDL Coder. Generated UVM verification environments may be used with Siemens® ModelSim® or Questa®, Cadence® Xcelium™, or Synopsys® VCS®.

In some applications of UVM verification, you may prefer to generate individual UVM components rather than complete UVM environments from MATLAB or Simulink. To generate individual UVM components from MATLAB, you can use UVM templates for predictor, sequence, or scoreboard components. In a similar fashion, you can generate UVM components for sequences, predictor, or scoreboards from Simulink subsystems.

If you are using the UVM Framework to develop UVM verification environments, you can use ASIC Testbench to generate SystemVerilog DPI components within a UVM Framework Workflow

Diagram showing how parts of a Simulink model can be generated into a SystemVerilog U V M environment using H D L Verifier, such as a U V M Sequencer, a U V M Scoreboard, and a behavior D U T

Perform UVM verification by generating a UVM testbench from a Simulink model.

For additional information, see HDL Verifier™.

Examples and How To

Generating UVM Verification Components and Environments

Generating SystemVerilog DPI-C Components with MATLAB for UVM Verification

Generating SystemVerilog DPI-C Components with Simulink for UVM Verification