HDL Verifier™ automates the verification of HDL code on Xilinx® FPGA boards by enabling FPGA-in-the-loop (FIL) testing. FIL testing helps ensure that the MATLAB® algorithm or Simulink® design behaves as expected in the real world, increasing confidence in your silicon implementation. The MATLAB algorithm or Simulink model is used to drive FPGA input stimuli and to analyze the output of the FPGA. With FIL testing, you can verify your design at FPGA speeds, enabling you to run more extensive sets of test cases and perform regression tests on your design.
HDL Verifier supports FIL verification over the Gigabit Ethernet interface for select Xilinx FPGA boards with Virtex®-7, Kintex®-7, Artix®-7, Spartan®-6, Virtex®-6, Virtex®-5, Virtex®-4, Zynq®-7000 SoC, and Kintex® UltraScale™ devices.
See the hardware support package system requirements table for current and prior version, release, and platform availability.
View enhancements and bug fixes in release notes.
Related Hardware Support Views: Aerospace and Defense, Automotive, Avnet, Communication Infrastructure, Consumer Electronics, FPGA Design, HDL Verifier, Industrial Automation and Machinery, MathWorks Supported, MATLAB Product Family, Medical Devices, Simulink Product Family, Support Package Installer Enabled, Xilinx
Support Package Installer installs this support package. To start the installer, go to the MATLAB toolstrip and click Add-Ons > Get Hardware Support Packages. For more information, read the documentation.
One of the following Xilinx® boards: