AXI Manager

Access AXI subordinate memory on FPGA board from MATLAB^® or Simulink^®

Note

MATLAB AXI master has been renamed to AXI manager. In the software and documentation, the terms "manager" and "subordinate" replace "master" and "slave," respectively.

Access on-board memory locations from MATLAB or Simulink by using the AXI manager IP in your FPGA design. This IP connects to subordinate memory locations on the board. The IP also responds to read and write commands from MATLAB or Simulink, over JTAG, PCI Express^®, or Ethernet cable.

Functions

`setupAXIManagerForVivado`	Add AXI manager IP path to Vivado project
`readmemory`	Read data out of AXI4 memory-mapped subordinates
`writememory`	Write data to AXI4 memory-mapped subordinates
`release`	Release JTAG or Ethernet cable resource
`copyImageToHostSDCardPath`	Copy board-specific SD card image files to host SD card location
`loadImageToTargetSDCardPath`	Load board-specific SD card image files to target SoC device SD card location
`loadBitstream`	Load custom FPGA bitstream and corresponding DTB file to target SoC device

Objects

aximanager Read and write memory locations on FPGA board from MATLAB

Blocks

AXI Manager Read	Read memory locations on FPGA board from Simulink
AXI Manager Write	Write memory locations on FPGA board from Simulink

Topics

Set Up AXI Manager
High-level steps for accessing memory-mapped locations on an FPGA board from MATLAB or Simulink.
JTAG AXI Manager
Integrate and configure JTAG AXI manager.
Ethernet AXI Manager
Integrate and configure Ethernet AXI manager.
Ethernet AXI Manager for Xilinx Zynq SoC Devices
Configure Ethernet AXI manager for Xilinx Zynq SoC devices.
PCI Express AXI Manager
Integrate and configure AXI manager IP over PCI Express.
Use Simulink to Access FPGA Locations
Access memory-mapped locations on an FPGA board from Simulink.
AXI Manager Simulation
Simulate AXI manager using the Vivado simulator.

Featured Examples

Access FPGA Memory Using JTAG-Based AXI Manager

Use JTAG-based AXI manager to access the memories connected to the FPGA. In the FPGA, there is a Xilinx® DDR memory controller and BRAM controller exist for accessing the DDR memories and the BRAM, respectively. These memory controllers provide an AXI4 subordinate interface for write and read operations by other components in the FPGA. The JTAG-based AXI manager feature provides an AXI manager component that you can use to access any AXI subordinate IPs in the FPGA. This example demonstrates how to integrate AXI Manager IP into a Xilinx Vivado® project and how to write and read data from the DDR memory and the BRAM using MATLAB®. This example simulates the design using the Vivado simulator and then programs the FPGA and performs write and read operations from the MATLAB console.

Open Script

Access DUT Registers on Xilinx Pure FPGA Board Using IP Core Generation Workflow

Use the HDL Coder™ IP core generation workflow to develop reference designs for Xilinx® parts that do not use an embedded ARM® processor present but that still utilize the HDL Coder generated AXI interface to control the design under test (DUT). This example uses the HDL Verifier™ AXI Manager IP to access the HDL Coder generated DUT registers from MATLAB®. Alternatively, you can use the Xilinx JTAG AXI Master to access the DUT registers using Vivado® Tcl console by writing Tcl commands. For the Xilinx JTAG AXI Master, you must create a custom reference design. The FPGA design is implemented on the Xilinx Kintex®-7 KC705 board.

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Perform Large Matrix Multiplication on FPGA External DDR Memory Using Ethernet-Based AXI Manager

Use Ethernet-based AXI manager to access external memory connected to an FPGA. This example also shows how to:

Open Example

Access FPGA Memory Using Ethernet-Based AXI Manager

Use Ethernet-based AXI manager to access internal and external memories of FPGA through different UDP ports. In the FPGA, Xilinx® DDR memory controller and BRAM controller exist for accessing the DDR memories and the BRAM, respectively. These memory controllers provide an AXI4 slave interface for write and read operations by other components in the FPGA. Ethernet-based AXI manager provides an AXI manager component that you can use to access AXI subordinate IPs in the FPGA. This example demonstrates how to integrate Ethernet-based AXI manager into a Xilinx Vivado® project and how to write and read from the DDR memory and the BRAM using MATLAB®.

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Access FPGA External Memory Using AXI Manager over PCI Express

Use AXI manager over PCI Express® (PCIe) to access the external memory connected to an FPGA. The FPGA includes a Xilinx® DDR memory controller for accessing the DDR memory. This memory controller provides an AXI4 slave interface for write and read operations by other components in the FPGA. The PCIe AXI manager feature provides an AXI manager object that you can use to access any memory mapped location in the FPGA. This example shows how to integrate PCIe AXI manager into a Xilinx Vivado® project and write and read data from the DDR memory using MATLAB®.

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Leverage Built-In Ethernet on Zynq to Perform Memory Access Using AXI Manager

Shows how to use an Ethernet-based AXI manager to access the external memory and FPGA IPs on the Xilinx® Zynq®-7000 ZC706 board over Ethernet. In Xilinx Zynq-based designs, MATLAB® acts as an AXI manager and communicates with the external memory controller and FPGA IPs through an AXI Lite interface by using the user datagram protocol (UDP) server in the processing system (PS). This block diagram shows the communication between a host and a Xilinx Zynq-7000 board over Ethernet.

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